Technology news
07/01/2007
Inside IBM’s airgap process
Airgaps have long been considered as structures to increase the speed of on-chip IC interconnects, though no one had developed manufacturing-worthy process flows. Only in the last year have companies such as Philips (now NXP) shown overviews of likely airgap manufacturing processes, albeit without production commitments. Now IBM has invented a new variation on airgaps that uses a self-assembling polymer mask layer as part of the process flow, and claims this can be a simple drop-in addition that adds only ~1% to chip cost for each dielectric layer gapped. Thus, for an advanced multilevel interconnect, a ~5%-8% cost adder should provide 35% faster chips or 15% less power consumption.
Circuit speeds are limited by the dielectric constant (k) of the insulating material surrounding metal lines, so industry roadmaps have focused on ever lower k dielectric materials. Unfortunately, materials engineering for a new dielectric material is difficult and expensive, and despite tremendous efforts and many false starts over the years, most of the world has now settled on SiCOH by CVD as the dielectric material (k~3) that provides acceptable cost, yield, and reliability. So-called ultralow-k (ULK, a.k.a. “extreme low-k”) films are typically k~3 SiCOH with the addition of ~10%-40% by volume of nanopores to reach k~2.5-2.2. More nanopores cannot be added without degrading yield and reliability, so the only practical way to get to k~2 is to incorporate a single large pore with clever processing as an “airgap.”
A multiyear development effort to create a manufacturable airgap process was led by IBM fellow Dan Edelstein, manager of BEOL technology strategy, who provided SST with exclusive insight into how IBM achieved these remarkable results. He explained that unlike previously known airgap process flows, the IBM approach starts with a standard dual-damascene copper and SiCOH dielectric process that has been in production for years. Airgaps are formed using a multistep etch, using a hardmask patterned with either self-assembling monolayers or standard lithography, depending upon the geometry of the interconnect.
While self-assembly can be used to make an array of nominally 20nm holes by spin-coating and baking, these holes merely pattern the hardmask that is used to etch the gaps into the dielectric, explained Edelstein. A noncritical lithography step is used to block out circuit areas that do not need gaps, he said. The self-assembly layer is not used to pattern the airgap hardmask at upper levels of the interconnect. “At some point in the hierarchy, it becomes more viable to use lithography instead of self-assembly,” he said.
While IBM doesn’t use airgaps for the first level of metal, they could be used at any of the higher levels within the hierarchical interconnect stack, Edelstein noted. “Most chips won’t need airgaps on all levels, but perhaps on half,” he said.
No matter the level, a special three-step etch process to form gaps with narrow top openings is the key to this process (see figure). “We etch a narrow channel down so it will cap off, then deliberately damage the dielectric and etch it so it looks like a balloon,” he explained. “You have a big gap with a drop in capacitance and then a small slot that gets pinched off.”
Starting with dual-damascene copper lines/vias and SiCOH single-phase dielectric, the essential IBM airgap process flow is as follows:
- Deposit hardmask;
- Spin-coat an imaging layer; either special new diblock polymer or standard photoresist;
- Create holes using either the self-assembly properties of the diblock or standard lithography;
- Block out circuit areas to not be etched using noncritical photolithography;
- Transfer holes from the imaging layer to the hardmask;
- Three-step etch sequence: anisotropic RIE to form columnar openings into SiCOH, then plasma damage of the column sidewalls, then isotropic wet etch to remove most of the remaining SiCOH below the hardmask;
- Strip hardmask; and
- PECVD of the next SiCOH dielectric level to cap the gaps with a classic “pinch-off” shape.
Since the self-assembling mask layer is not aligned to the underlying interconnect structures, and since the block-out mask is “noncritical” to save costs, the hardmask will inevitably expose the tops and sides of some metal lines to RIE. Consequently, the SiCOH etch chemistry needs to have excellent selectivity so that it does not attack copper or any metallic barrier layers. Edelstein says that they’ve been able to work with standard gas precursors for this critical RIE step.
The new airgap process is an optional loop off of the standard flow, so designers can choose to use airgaps at any of the levels in the on-chip interconnect hierarchy-and IBM also has developed an automated algorithm for making the block-out mask. “As a customer you can turn on the airgap option for any level on any chip,” Edelstein told SST. The ability to add airgaps as a “drop-in” to an existing on-chip interconnect process flow minimizes risks, and explains the company’s confidence that this flow will be used in manufacturing by 2009.
The diblock polymer is a significant part of this airgap process. IBM Almaden Research developed this material for broad applications in fabs-it’s like a standard photoresist in terms of handling and dispensing; it has a wide process window; and IBM has detected no shelf-life problems for up to one year.
Using self-assembly in coordination with lithography opens up new possibilities in general for integrated process flows, so look for news of additional applications in coming years. “We hope that we can use directed self-assembly to get to other device features,” said Edelstein. “This is just the tip of the iceberg.” -E.K.
Check out SST’s exclusive audio interview with IBM’s Edelstein at sst.pennnet.com/podcasts.
Virtuous cycle: Growing Japanese solar market attracts new suppliers
Japan’s burgeoning solar market (see figure, p. 28) is attracting new players with new technologies, and that’s helping to bring down costs to spur further growth. The two big new players about to muscle in to the solar cell business are banking on innovations in equipment and materials for their success.
“We’re aggressively adopting new equipment and materials because our style is to do what no one else does,” Yasuhiro Suzuki, who’s in charge of Honda Soltec’s solar cell development, told SST’s partner Nikkei Microdevices. Honda reportedly will use coating tools adopted from the automotive industry-not a vacuum process-for the CIGS thin film cells it will start producing later this year at a new 27.5MW plant. Fuji Electric officials also say they’re aggressively adopting new materials to distinguish the amorphous silicon cells on flexible film they’re now sampling.
Suppliers from a range of other fields are stepping up with offerings to the more mainstream crystalline silicon solar cell makers-new types of lower cost silicon, more efficient wire saws, and better encapsulants-to drive down the price of solar energy. JFE Steel provides polysilicon made by a metallurgical process that drives off the impurities in the silicon (first with an electron beam in a vacuum, then with a plasma torch in an argon atmosphere) and refines and cools the melt in a continuous process similar to steelmaking. These metallurgical polysilicon furnaces can be brought online in small increments relatively quickly and cheaply, though they do turn out product of only “six nines” (99.9999%) purity-less than the eleven nines of the conventional Siemens process, but apparently sufficient for at least current-generation solar cells.
Chisso Corp. is reviving an improved version of its old zinc reduction process for making polysilicon of “seven nines” (99.99999%) purity, which costs slightly more than the metallurgical process, but still costs 30%-40% less than the Siemens method. The chemical maker has formed a venture with Nippon Mining Holdings and Toho Titanium to commercialize the process, now in pilot production and yet to be demonstrated in high volume. Chisso’s process reacts the molten Si with Cl2 to make SiCl4, and then reduces the SiCl4 with Zn vapor to get polysilicon, with ZnCl2 as the byproduct. This ZnCl2 is then recycled back into Cl and Zn to feed back into the reaction, using Toho Titanium’s molten salt electrolysis technology.
 Planned ramp of solar cell capacity in Japan is starting to be measured in gigawatts. (Source: Sanyo Electric, Nikkei Microdevices) |
Other suppliers are finding ways to reduce the amount of silicon wasted from sawing the silicon ingots or blocks into wafers with the typical 0.14-0.16mm wire. Yasunaga Wire Saw Systems, which supplies saws using ultrathin 0.07mm wire and tight uniformity control to the compound semiconductor sector, saw that the solar customers buying its slurry reclamation systems (accounting for some 80% of the company’s systems for recycling polishing slurry) needed better saws as well. So it introduced a commercial solar silicon wire saw in April that uses 0.12mm wire to cut two 125mm × 125mm × 280mm ingots at the same time, reportedly yielding 6.8% more useable silicon than 0.14mm wire, and increasing output from 1436 to 1534 wafers.
Mitsubishi Electric, a major supplier of wire electrodischarge machining systems for precision cutting, is now applying that technology to the solar industry as well. The technology uses the heat from a pulse discharge between the wire and the substrate to melt and cut the substrate precisely, without contact. Though wire electrodischarge does precision cutting well and eliminates the need for abrasive slurry, it has typically only worked for cutting metals where it’s easy to get the pulse discharge. Mitsubishi gets the process to work with silicon as well, by using a high frequency, single-pole source. The company reports that tests show exposing the wafers to the additional heat from this cutting process has no impact on conversion efficiency of the finished solar cells.
Meanwhile, Dainippon Printing (DNP) is applying its technology for food packaging plastics to solar cell encapsulants and backsheets. DNP says its new thermoplastic olefin film is a significantly better water-vapor barrier than other heat-processed films, without needing the usual curing at 150°C for 30 min, and at no added cost. DNP reports that major solar-cell makers in Japan and abroad have qualified the material, and expects wide adoption after it ramps production during the middle of this year. -Dr. Paula Doe, Contributing Editor
A single-nanowire positioning system for testing properties
Researchers at the National Institute of Standards and Technology (NIST) say they have created a method for manipulating and positioning individual nanowires on semiconductor wafers, enabling fabrication of test structures using only optical microscopy and conventional photolithographic processing.
Today’s smallest-diameter nanowires are assembled atom-by-atom in a “bottom-up” bulk growth process, e.g. through CVD, which creates “haystacks” of nanowires of varying lengths and diameters, according to NIST. The traditional approach is to “throw a whole bunch of these down on the test surface, hunt around with a microscope until you find a good-looking wire in about the right place, and use lithography to attach electrical contacts to it,” said NIST electronics engineer Curt Richter, in a statement.
The new process, using a modified probe station with a high-resolution optical microscope, positions work surfaces under a pair of customized titanium probes, each with <100-dia. tips (see figure). Silicon nanowires suspended in a drop of water are deposited on a staging wafer patterned with tiny posts; once dried, the nanowires are left sitting on top of these posts, and can be picked up by the probe tips using static electricity. The test structure wafer is positioned under the probes, and the wafer and/or probe tips are moved until the nanowire can be placed on the desired position.
While admittedly “not at all suited to mass production,” the process does have potential application in creating elaborate structures to test nanowires’ properties, NIST says. The group has already built a multiple electrical-contact test structure to measure nanowire resistance independent of contact resistance, as well as an electromechanical switch to measure the nanowires’ flexibility. -J.J.M.