Process monitoring methodology using in-line parametric test
07/01/2007
Some of the device defects that are coming to the fore at advanced technology nodes are due to shrinking linewidths that cause greater interaction between device lines. These interactions can lead to cross-talk, larger interconnect resistance, and leakage-all of which impair device performance and yield. Smaller geometries result in critical layers with atomic-layer thicknesses that still need to maintain their electrical characteristics across the wafer and from wafer to wafer. Smaller feature geometries also result in vias and trenches with higher aspect ratios, resulting in buried defects that are difficult to find with surface defect inspection tools.
Today, there are well-established methods of testing wafers after they have finished being processed in order to measure the parametric performance of each device. Generally, these involve the use of specially designed test structures, wafer probe cards, probers, and automated parametric test equipment. This end-of-line testing is ideal for qualification and feedback on the quality of the wafer fabrication process for yield improvement.
IC manufacturers, however, ideally also want to be aware of parametric issues that arise as the wafer is being processed so that they can quickly isolate the source and make corrections. They want to lessen the risk of lower yields on future wafer lots and reduce the number of scrapped wafers needed to maintain profitable fab operation. Process tools are monitored for excursions using blank monitor wafers or in-line on product wafers. Blank wafer-based monitoring is expensive and does not always replicate stack conditions on a product wafer.
Methods for conducting parametric test in-line may involve the use of optical or electron-beam metrology systems that measure multiple parameters and correlate the information to actual parametric performance. These metrology systems provide only indirect parametric measurements, which may prove insufficient. For example, a poor etching process may leave behind a very thin metal whisker that causes bridging between the gate metal and drain or source metal of a transistor. Another example is a void in the bottom of a via. Such hidden electrical defects may not be detected with optical methods because of limitations in resolution. Other methods that can provide direct measurements of process sensitive parameters, such as threshold and breakdown voltage, leakage current, sheet resistance, and via chain resistance, are highly destructive to product wafers.
New challenges in e-testing
In-line electrical test via wafer probing can provide many benefits, including rapid parametric measurements, as well as the discovery of fatal defects that may not be detected with optical methods. However, while wafer probing has been used for in-line e-test for more than a decade, its effectiveness in high-volume manufacturing environments has been severely limited by the probe card, which has traditionally utilized cantilever, or needle-based, probes.
The greatest challenge with cantilever probes has been contamination, which is produced when the probe contacts the wafer’s metal layer to take measurements. Contamination can lead to decreased wafer yields. The current best practice implemented in wafer fabs to address this problem is to clean the probe card after every touchdown on the wafer. However, the cleaning process can take several minutes-resulting in an extremely low test throughput. In addition, re-testing is often needed due to poor contact between the cantilever probes and the target area on the metal layers.
A new probe-card technology developed by FormFactor uses micromachining/microelectromechanical systems (MEMS) manufacturing processes to produce small probe tips that provide highly-accurate and repeatable parametric measurements at in-line process monitoring. Since the probe tips are manufactured using processes similar to semiconductor manufacturing, they are highly scalable.
 Figure 2. Comparison of measurement stability by probe card type. |
The probe architecture leverages a combination of metal beams and metal posts to provide low contact force. Low contact force is important in minimizing the amount of digging into the metal layer during probing, which prevents the production of contaminants. It is also important in preventing the destruction of film layers-especially porous low-k interlayer dielectrics underneath the metal layer upon which the probing takes place (Fig. 1).
Figure 2 shows an example of in-line leakage current measurement data provided by two different probe card technologies-a traditional cantilever probe card and the advanced MEMS-based probe card-on the same process and same parametric tester. Measurement data provided by the cantilever probe card fluctuates significantly. In addition, the cantilever probe card requires frequent cleaning of probe tips and re-test when measured values exceed the statistical process control (SPC) limits.
Two possible causes for the wide deviation of measured data using a traditional cantilever probe are: 1) unexpected current flow path made on the wafer by metal debris produced by high-contact-force probing; and 2) slip-off of probe tips from the target area of metal layers due to poor tip placement accuracy. In the latter case, frequent rubbing by the cleaning sheet, coupled with the mechanical stress from the high duration of touchdowns needed for volume parametric test applications, eventually causes cantilever probe tips (that are manually placed and adjusted into the probe head) to move out of position for the target metal layers.
In contrast, the MEMS-based probe card shows stable measurement data (Fig. 2). The small probe tips (12μm × 12μm, typically) on the MEMS-based probe have high tip placement accuracy that enables a secure contact and positioning of the small target metal layers. Additionally, the low contact force eliminated metal debris and enabled a steady contact resistance. Results of a wafer re-test study conducted at a leading memory manufacturer also demonstrated that over the course of three million wafer probe touchdowns, the re-test frequency of MEMS-based probe cards was 30 times less than for cantilever-based probe cards.
In-line e-test using MEMS-based probe cards can take a few minutes per wafer to obtain parametric data versus optical in-line tools, which generally take an hour.
Conclusion
In this paper, an alternative approach to in-line parametric metrology that leverages wafer probe card technology to take direct electrical measurements on product wafers quickly and non-destructively was introduced. The combined use of optical in-line metrology and in-line e-test is the optimal solution for collecting meaningful information and feeding back analyzed data for rapid improvement of process quality and yield.
Kazunori Nishitsuru is director of marketing, Parametric Test Product Group, at FormFactor K.K., Omori Bellport D, 9F, 6-26-3 Minami Oh-i, Shinagawa-ku, Tokyo, Japan 140-0013; ph 81/3-5767-6828, e-mail [email protected].
Nobuhiro Kawamata is senior director of marketing, Parametric Test Product Group, at FormFactor K.K.