It’s harder to refute the benefits of DFM
07/01/2007
As the semiconductor world moves toward 45nm geometries-with 32nm and 22nm processes on the horizon-relying on designers to follow recommended design rules in addition to the standard minimum rules is increasingly less effective for improving yield. This is where design for manufacturability (DFM) methodology can step in and help address issues caused by increasing process variation and shrinking process windows as manufacturing tools are pushed beyond their originally envisioned capabilities.
Production-worthy tools have physical limitations, so not using DFM means that traditional design rules and SPICE models will drive design guard bands that negate the cost and performance benefits of these advanced nodes.
The companies in the Common Platform technology alliance (Samsung, IBM, and Chartered Semiconductor) believe DFM can give customers added opportunity to improve yield by taking advantage of DFM methodology at lower risk, even though the methodology isn’t fully mature.
Examples of the benefits of DFM are already quantifiable at 90nm and 65nm nodes. Using DFM models for lithography simulation and critical area analysis (CAA), the Common Platform and its partners have adopted a methodology that designs standard cells and other IP blocks to minimum design rules, and then applies these DFM models. This design flow identifies and removes hot spots (areas where manufacturing variance may cause yield issues) with no area penalty over minimum design rules. In addition, linewidth variation is decreased, resulting in improved performance.
A study was done to compare the size and performance of DFM-designed cells to cells laid out following high-priority recommended rules and minimum rules. The resulting cells sizes were 0~25% smaller for the DFM-designed cells, depending on the complexity of the specific standard cell. DFM-designed cells exhibited delay time reduction of ~5% from the original layout compared to DFM-modified layouts. Performance gains varied by cell complexity and are dependent on original design techniques. In a chip design, the die size area shrank by 7.6% compared to the die size produced with high-priority recommended rules.
At the full chip level, the Common Platform alliance has developed reference flows with leading EDA companies that make use of CAA DFM techniques such as via doubling and wire spreading to exploit white space in the interconnect-again, with no area penalty. There have been designs manufactured in Common Platform fabs without using these techniques that went from very low yield to yielding on the expected defect density curve when via doubling and wire spreading were applied.
Common Platform partners will soon begin incorporating advanced model-based DFM into the routing flow when using 45nm processes, with efforts underway in lithography and CAA-aware routing. This work integrates Common Platform technology process models with third-party DFM tools and leading EDA reference flows.
Common Platform partners have seen no area penalties so far from using DFM methodology regardless of yield. Alliance members are performing DFM research in individual fabs, then gathering and sharing this data and creating new models for customers. With its focus on portability across fabs, the Common Platform is in an optimal position to produce quantifiable, credible data on DFM, just as it makes new DFM models available to all foundry customers while calibrating and sharing new process models with EDA solution providers.
Even though DFM is still in its early days and has a lot of room for improvement in ease of use, Common Platform partners believe there is already enough evidence to show it has merit. So far, as process geometries shrink, DFM is proving to be an important way for performance- and cost-sensitive companies to improve their potential for success.
Contact Ana Molnar Hunter, VP of Technology, Samsung Semiconductor Inc., 3655 N. 1st Street, San Jose, CA 95134, United States; e-mail [email protected].
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Ana Molnar Hunter, Samsung Semiconductor Inc., San Jose, CA, United States