Technology news
06/01/2007
Cooling chips to -33°C gains a one-generation jump in speed
Active cooling looks like a practical addition to the toolkit for increasing mainstream chip performance in the near term, claim Toshiba scientists who’ve been working out the details of designing low-temperature devices. Their work, reported to SST partner Nikkei Microdevices, demonstrates a 37% jump in speed by reducing internal operating temperature to -33°C, equivalent to shrinking the geometry by a generation. But they say it doesn’t take such extreme cooling to get a significant improvement-bringing the temperature down to just a warm room temperature of 27°C buys a 19% increase, or about half a generation. Even a 10°C reduction may give a 5% boost in speed.
Researchers Akira Hokazono, Shigeru Kawanaka, and Yoshiaki Toyoshima of Toshiba Corp. Semiconductor Co.’s Center for Semiconductor Research and Development, explain that the experiments use basic vapor compression refrigeration, with a small compressor and heat exchanger, and microchannels to move the coolant across the back of the chip (Fig. 1). They note that this involves no exotic technologies, so development costs should be modest compared to some other new approaches. New kinds of packaging will be needed to handle condensation once temperatures drop below 10°C or so-but if the packaging issues can be solved, the Toshiba group expects to use chips cooled to about 10°C in high-performance consumer chips for digital home servers at the 32nm node by 2012.
While plenty of other work on low-temperature transistors has looked at the theory and at cooling supercomputers, the Toshiba researchers focused on the nitty-gritty specifics of mainstream chip design and production. In so doing, they have demonstrated progress in solving several key practical problems, including finding ways to avoid the increase in threshold voltage and parasitic resistance that typically occur at low operating temperatures, and reducing device power consumption enough to make up for the additional energy used by the cooling system. They also showed that low-temperature operations had no adverse impact on the effectiveness of strained silicon and high-k gates, nor on the reliability of copper/low-k interconnects or on MOSFET hot carrier-induced degradation.
One key to practical low-temperature chip operation is determining the best threshold voltage, which requires tradeoffs not only between power consumption and performance, but also between power consumption for the circuit and that for the cooling system. These tradeoffs are all complicated by the fact that lowering the operating temperature raises the channel surface potential and increases the threshold voltage. Experiments determined a mid-range threshold voltage resulted in the lowest energy usage for the overall system, reducing standby power demands enough to make up for the increase in power needed to cool the system to the optimal temperature.
To prevent the threshold voltage from increasing beyond this optimal level at lower temperatures, researchers turned to forward body bias. A forward body bias of 0.4V or higher prevented an increase. At low temperatures, forward bias could in fact be increased more than in standard CMOS, up to 0.8V or higher. Both fully depleted SOI and finFET structures were effective in maintaining the desired threshold voltage at low temperatures.
Another problem at low temperatures is the increase in parasitic resistance. Here the Toshiba group found that most of the resistance occurred in the pMOS region of the silicide and silicon interface, and this could be prevented by high-dose (2×) doping. Some resistance-increasing carrier freeze-out did start to occur below -150°C, but it was not an issue in the less extreme -33°C temperature range under consideration.
Low temperatures appear to have little impact on the performance of current materials. Strained silicon on implanted SiGe continued to show the same 60% improvement in mobility at -196°C. Performance of both pMOS and nMOS high-k gate transistors increased linearly as temperatures decreased from 125°C to -196°C (Fig. 2).
Reliability tests also were encouraging. Degradation in transistor performance from high-energy carriers at lower temperatures was a concern, but Toshiba reports there was no degradation for nMOS, and adding forward bias to prevent the threshold voltage increase countered the hot carrier degradation in pMOS in the temperature range of interest. Simulations showed that low-k interconnect materials with high heat expansion coefficients might shrink at low temperatures and distort contact plugs and interconnect layers, but patterned wafers showed no increase in via resistance, and no higher failure rates from stress-induced electromigration after repeated cycling through 10 hours at -196°C. -Paula Doe, Contributing Editor
Going deep: New capacitor trench etching enables sub-70nm DRAMs
The need to control DRAM cell capacitance and ensure that this parameter is uniform across all cells on the wafer becomes more critical to memory manufacturers as they hit 70nm structures requiring ~80:1 aspect ratios. For DRAM applications, the volume of the trench (i.e., the depth and width) determines the capacitance of the DRAM cell-the deeper the trench, the higher the capacitance. The requisite across-wafer capacitance is enabled by having good selectivity to the hard mask, which allows the etching to go deep. Applied Materials is targeting both requirements with its Centura Mariana Trench Etch tool.
The new etch chamber is based on traditional MERIE (magnetically enhanced reactive ion etch) technology with some additions, such as a 60MHz bottom source as opposed to placing the source in the lid. Declan Scanlan, head of deep-trench KPU within Applied’s conductor etch division, told SST that the company’s plasma studies answered two key questions: 1) whether putting the source power through the bottom instead of the top would be more efficient at coupling the power into the plasma, and 2) whether it could be made uniform. The studies revealed “a significant improvement in plasma uniformity when we went from a top source to a bottom source,” Scanlan said. With respect to efficiency, the modeling also showed that the content of the species in the plasma “was basically the same between top and bottom sources.”
 Over 70% of the PECVD for 45nm node logic are for films &less;100nm thin, calling for different OEM tools to optimize fab throughputs. (Source: Novellus Systems) |
Process control is provided by Applied’s interferometric endpoint detection technology (trademarked as “EyeD”), which measures the amount of hard mask that remains. “Because we can measure the remaining mask, we can squeeze every inch of trench depth out of each wafer because we can stop exactly where needed, so we’ve eliminated the safety margin that had been needed,” Scanlan noted.
The etch system’s gas injection has two process uniformity tuning knobs; dual-zone gas injection allows the user to flow different gases into the center of the wafer vs. the edge of the wafer. Additionally, an independent gas injection enhancement provides for the direct flow of one or two gases to the edge of the wafer-without flowing any into the center of the wafer-making up for the differences between the center and the edge of the wafer. -D.V.
MRS meeting specs the future
This year’s spring meeting of the Materials Research Society (MRS, April 9-13 in San Francisco) informed a record number of attendees on near- and far-term possibilities for process technology, showcasing research results in electronic materials development: CMOS high-k gate dielectrics, nano-imprint lithography, organic semiconductors, quantum dots, and nano-tubes-and wilder technologies like neuro-prosthetic interfaces and designs based on structures created by Mother Nature.
Sachin Joshi of UT-Austin showed that hybrid-orientation technology silicon wafers, based on the MEMC direct silicon bonding approach, contain inherent defect-rich junctions between orientations. Shallow-trench isolation regions 60-140nm wide may be used to eliminate these defects, though this seriously limits circuit density, he pointed out. Nonsilicon channels will probably also limit density, so their use will probably be limited to RF and mixed-signal applications in small portions of chips.
Arief Budiman from Stanford analyzed the grain orientation in submicron damascene copper lines using the synchrotron x-ray beam from the ALS Berkeley Lab. This very bright x-ray source and submicron spot-size (0.8µm × 0.8µm) allows for resolution of crystal bending/stress as well as the dislocation density. Starting with large single grains spanning across the width of the line (“bamboo structure”), Budiman’s group observed clear directionality of EM-induced plasticity and thus the orientation of slip-planes. They found that <112> orientations were most susceptible to plastic deformation, so any grains with such orientations that line up with the induced EM-stress will deform. Grain orientation controls plasticity, which in turn influences EM degradation mechanisms and circuit reliability.
An analysis of the influence of microstructure on void formation in failed copper interconnects, from Intel’s Sadasivan Shankar, revealed that voids first nucleate at triple-boundaries caused by stress-induced de-cohesion at copper interfaces. These voids can be easily pinned by a grain boundary, which provides a fast diffusion path for the void to grow across the width of a line or via. “It almost unzips the grain-boundary,” he commented. A 2D model developed with Brown and UT-Austin accounts for current flow and stress, diffusion along surfaces and interfaces, void migration, and the interaction of voids and grain boundaries.
Duane Boning, the MIT professor who created one of the first useful pattern-density step-height CMP models in the 1990s, showed progress on new physically based models. By explicitly including pad properties-elastic response (including lateral coupling across the pad), slurry transport, and average asperities-he showed how chip-scale uniformity can now be predicted.
Roland Rzehak of Qimonda in Dresden, Germany, provided both an overview and details of inexplicable CMP removal-rate variations using ceria slurries. A counter-intuitive “slow-start phenomena” slows the removal rate for the first minute of pattern planarization to be ~2.5× lower than that for blanket films. Ceria particles may initially adsorb in trenches to take some of the pressure load. However, Qimonda observes additional non-uniformities implying influences of pattern pitch, the pad material, and possibly effects from chemical additives to the slurry.
MRS meetings also cover wilder technologies such as superconductors, neuro-prosthetic interfaces, and “the nature of design using nature’s portfolio” like the self-assembly of seashells or the nano-hairs of gecko feet. Materials scientists and engineers continue to explore the structure-property relationships of the physical world, and confirm that there is indeed “still plenty of room at the bottom.” -E.K.
Diving deep for device inspiration
The 3D shells of tiny ocean creatures called diatoms could provide the foundation for novel electronic devices, including gas sensors able to detect pollution faster and more efficiently than conventional devices, according to research reported in Nature by the Georgia Institute of Technology.
Using a chemical process that converts the shells’ original silica (silicon dioxide, SiO2) into silicon, researchers have created a new class of gas sensor that utilizes the diatoms’ unique and intricate shells (see figure). The converted shells, which retain the 3D shape and nanoscale detail of the originals, could also be useful as battery electrodes, chemical purifiers, and in other applications requiring complex shapes that nature can produce better than humans.
 A sensor created from a microporous silicon structure converted from the shell (frustule) of a single diatom. (Source: Georgia Tech) |
“When we conducted measurements for the detection of nitric oxide, a common pollutant, our single diatom-derived silicon sensor possessed a combination of speed, sensitivity, and low-voltage operation that exceeded conventional sensors,” characteristics enabled by the diatom-derived shape, high surface area, and nanoporous nanocrystalline silicon material, noted Kenneth Sandhage, a professor in Georgia Tech’s School of Materials Science and Engineering.
According to the Georgia Tech paper, roughly 100,000 species of diatoms exist in nature, and each forms a microshell with a unique and often complex 3D shape involving cylinders, wheels, fans, donuts, circles, and stars. Sandhage and his research team have worked for several years to take advantage of those complex shapes by converting the original silica into more useful materials, toward an ultimate goal of converting genetically modified diatoms to generate microshells with tailored shapes.
Because solid silicon replicas cannot be directly produced from silica structures with conventional processing, which requires temperatures well above the silicon melting point of 1414°C, the researchers used a reaction based on magnesium gas that converted the silica of the shells into a composite containing silicon and magnesium oxide at only 650°C, which allowed preservation of the complex channels and hollow cylindrical shape of the diatom. The magnesium oxide, making up about two-thirds of the composite, was then dissolved out by a hydrochloric acid solution, which left a highly porous silicon structure that retained the original shape. The structure was then treated with hydrofluoric acid to remove traces of silica created by reaction with the water in the hydrochloric acid solution.
Researchers connected the individual diatom-derived silicon structures to electrodes with an applied current, and used them to detect nitric oxide. The highly porous silicon shells, which are about 10µm in length, could also be used to immobilize enzymes for purifying drugs in high-performance liquid chromatography and as improved electrodes in lithium-ion batteries. The produced silicon also was shown to be photoluminescent, so the fabrication process may have interesting photonic applications as well.
Though Sandhage and his colleagues have demonstrated the potential of their technique, significant challenges still need to be addressed. The sensors will have to be packaged into useful devices, for example, connected into arrays of devices able to detect different gases, and scaled up for volume manufacturing. Also, further research is needed to learn how to manipulate the genome of the diatom and precisely alter and control the structures produced.
Since scientists already know how to culture diatoms in large volumes, harnessing the diatom genetic code could allow mass production of complex and tailored microscopic structures. Other Georgia Tech scientists are currently working on ways to enable genetic engineering of diatom microshell shapes.
The Aulacoseira diatoms used in the research were millions of years old, obtained from samples mined and distributed as diatomaceous earth. Sandhage’s group has set up a cell culturing lab, with the assistance of other Georgia Tech colleagues, to grow and provide diatoms samples with other geometries. The work is sponsored by the US Air Force and Naval research offices.-J.M., J.J.M.