Merging mask design and manufacturing to drive cycle-time improvement
06/01/2007
Semiconductor industry observers who think the drive for lower manufacturing costs and cycle time is a recent phenomenon would do well to acquaint themselves with the history of the data handoff between design and manufacturing. This handoff, from designer to mask manufacturer to wafer fab, has undergone constant change to accommodate the ever-decreasing value of k1, while obeying the demands of costs and cycle time.
In principle, the wafer print closely resembles the design data, and before OPC began to creep into lithography about 10 years ago, this meant that the mask should mimic the design data, too (or, perhaps more precisely, that the wafer print should resemble the mask). Mask manufacturers performed data sizing to correct mask process-bias effects, but they generally avoided other data handling. File sizes were modest; MEBES (manufacturing electron beam exposure system) was the dominant mask-writing-tool data format. The vast majority of mask writers used raster scanning, and mask write time had little relationship to data density or file size. Often, designers sent “write-ready” data (pre-sized data fractured into the mask-writing tool format) to their mask suppliers to minimize mask cost and cycle time. Neither mask manufacturers nor chip designers needed to know much about wafer lithography. The mask was truly part of manufacturing.
The 180nm technology cycle ushered in substantial change: k1 dropped below 0.5, driving the introduction of rules-based OPC. The mask and wafer print were no longer scaled, identical twins, and the task of changing the mask design to correct wafer print effects seemed to fall naturally to the designer.
Mask design was (and is) effectively executed in the GDSII file format familiar to those working in the backend of design. Most mask writers were still raster scanned and used the MEBES data format, and files were still converted to MEBES format for mask manufacturing. However, OPC increases file size, so the data-transmission time to the mask shop became a challenging issue. GDSII became popular for data transmission, reducing the amount of write-ready data and shifting some of the data-manipulation load from the designer to the mask manufacturer.
At the 130nm technology cycle, variable shaped electron beam (VSB) mask-writing tools became popular, bringing with them new data formats. Even more significant was that the writing time (hence, cost-of-ownership) of a VSB tool depended on data density, file size, and fracture quality, all of which are affected by OPC. This complexity demanded data optimization from the mask manufacturers.
Extending into the 90nm technology cycle, the introduction of mask-process compensation (correction for mask-process effects, such as line-end shortening and through-pitch bias) and mask rules checking opened the mask manufacturers’ doors to EDA software previously used only by design-verification and mask-design groups. Mask manufacturers and mask designers were using the same software suites for parallel purposes: for mask lithography and for wafer lithography.
Over the past several years, model-based OPC has been introduced by EDA software suppliers and is now common for wafer OPC, regardless of design rules. Model-based OPC can account for lithography limitations more accurately than rules-based OPC, but it is also computationally intensive.
Faced with cost and cycle-time pressures, some semiconductor companies are partnering with their maskmakers to merge mask design and mask manufacturing. In the basic approach, the mask manufacturer designs and builds the mask. In one variation, the mask manufacturer performs OPC model calibration and maintenance, working closely with the wafer fab to ensure a stable, robust lithography process. In another variation, the wafer fab maintains the OPC model and provides it to the mask manufacturer as a locked file, which the mask manufacturer uses to perform mask design. In both cases, there are cost and cycle-time advantages because the mask design, data preparation, fracture, and rules checking are executed in one step.
The semiconductor industry continues to mature with an eye toward cost and cycle-time improvement. The evolution of mask design and mask manufacturing into their current “natural fit” is an excellent example of this maturation.
Acknowledgment
MEBES is a trademark of Applied Materials.
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Franklin Kalk
Toppan Photomasks Inc.,
Round Rock, TX, United States