Using strain engineering to improve NVM retention time
06/01/2007
Conventional CMOS logic device scaling beyond the 90nm node requires local strain engineering to increase electron and hole mobilities and enhance transistor performance [1-4]. In addition to increasing mobility, which has some advantages in nonvolatile memory (NVM), strain also alters the SiO2/Si barrier height, the conductivity mass perpendicular to the SiO2 interface, and electron trap energy levels, all of which will alter the retention time.
 Figure 1. Flexure-based wafer bending jig a) photograph, and b) schematic diagram. |
The charge retention characteristics of an NVM cell are set by the leakage of stored electrons under specified environmental and operational conditions including power-off mode. For the NVM NAND cell, electrons are generally stored on a floating poly-Si gate, while for NOR, electrons are stored on a floating gate or in nitride traps. With NVM technology in the nanoscale regime, many process steps from cell isolation formation to packaging introduce both intentional and unintentional strain in the floating gate, insulating layers, and channel. There have been early reports on the importance of minimizing compressive stress since it degrades retention time [5, 6].In this study, we investigated the effect of tensile and compressive stress on floating-gate and nitride trap-based NVM retention time. This has applications for intentionally engineering “good” types of strain and removing “bad” types from an NVM process flow.
Experimental model
A flexure-based four-point bending setup was used in applying large amounts (up to 600MPa) of tensile and compressive stress, as shown in Fig. 1a. A flexure is a long beam with a notch on one end, which gives the beam only one degree of freedom [7].The setup has a system of eight such flexure beams, which provide uniaxial upward displacement to the bottom rods in a traditional four-point bending setup, as shown in the schematic in Fig 1b. This eliminates error due to the uneven rotation of two screws present in traditional four-point bending setups and is essential for achieving high stress. The surface stress along the channel direction is calculated from the relationship:
 |
where E is the Young’s Modulus (E = 168GPa for {110} channel), y is the sample vertical displacement, t is the total thickness of the sample, L is the length of the sample between the two outer rods, and a is the distance between the inner and outer rods, as shown in the schematic in Fig. 1b. The jig was calibrated with a load cell under the mounting platform and a strain gauge was mounted onto the surface of the wafer.
Strain effect on data retention
To understand the effect of strain on retention time, we performed two experiments, both of which applied tensile and compressive stress longitudinal to the channel on industrial samples. The first experiment measured the change in the stress-altered leakage current for thick SiO2 tunnel oxides. The second directly measured the stress-altered retention of stored electrons in nitride traps.
In the first experiment, the change in strain-altered electron tunneling current was quantified by introducing compressive and tensile stress into the gate, oxide, and channel of a 1μm nMOSFET with a SiO2 oxide thickness of 55Å, which is typically used in NVM. The data were taken at room temperature on ten samples with a repeatability of within 5%. The channel direction of the nMOSFET was {110}, and a mechanical stress as large as 600MPa was introduced.
 Figure 2. Strain-induced change in gate tunneling current. Note uniaxial tensile stress reduces electron tunneling current while compressive stress increases the current. |
The results plotted in Fig. 2 show that the SiO2 tunnel leakage current increased under compressive stress and decreased under tensile stress. We also noted the leakage had a strong electric field dependence, thus the stress-altered change in the leakage current is much larger at low vertical fields (retention condition) than at high electric fields (program condition).
In the second experiment, since it is difficult to directly measure the leakage current from nitride traps, we measured the change in retention time for the trapped electrons on cells of various sizes. All cell programming was performed at room temperature using conventional programming conditions without any externally applied mechanical stress. Next, the samples were baked at 190°C for 24 hours with and without externally applied tensile or compressive mechanical stress. For each experiment, the stressed and unstressed samples were baked at the same time, and all devices were from the same wafer on neighboring dice. The threshold voltage shift after the bake condition is plotted in Figs. 3a and 3b. For all device sizes, tensile stress was observed to significantly improve the retention of the trapped electrons, while the opposite was observed for compressive stress. The magnitude of stress used in the experiment (a few hundred megapascals) is typical of stress intentionally/unintentionally induced on a Si channel of NVM-Flash cell via process steps.
Discussion
Severe degradation in the retention time has been reported for mechanical stress, leading to the suggestion that process-induced mechanical stress needs to be eliminated [6]. However, it is compressive stress that degrades retention time. Tensile stress offers improvement, which results from stress-altered changes in the SiO2/Si barrier height and out-of-plane conductivity mass in floating-gate memories and from changes in the trap activation energy in nitride trap-based memories. These effects are discussed in more detail below.
Strain alters tunnel oxide leakage currents by changing the SiO2/Si barrier height and the electron conductivity effective mass. The barrier height is altered via strain-induced changes in the Si and SiO2 electron affinities (Fig. 4= 0.19m0 being significantly smaller than the longitudinal mass (parallel to the axis) given by m= 0.98m0, where m0 is the free electron mass. For unstressed bulk silicon, the total electron conductivity mass m* is obtained by adding the contributions of the six degenerate valleys and is given by
 |
Assuming a crystal orientation where {001} is the floating gate to the channel direction, in-plane tensile stress reduces the tunneling current by removing the degeneracy between the four in-plane valleys Δ4 and the two out-of-plane valleys Δ2 by splitting them in energy. Tensile stress lowers the energy of the Δ2 valleys and results in preferential occupation of these states. The tunneling current in these states is significantly reduced due to m* transforming to m= 0.98m0 after enough band splitting to fully populate the Δ2 valleys. Furthermore, the Δ2 splitting increases the SiO2/Si barrier height, which will also decrease the tunneling current. Which effect dominates depends on the magnitude of the oxide field (Fig. 4).
Similarly, strain is known to alter the activation energy of SiO2 electron traps and should be expected to alter the retention time. For nitride-based memories, the primary electron loss mechanism at elevated temperatures is the thermal detrapping of the stored electrons.
The electron detrapping is proportional to exp(−Ea/kT), where Ea is the electron trap activation energy, and mechanical stress shifts the activation energy. Our data show that 100 MPa compressive stress decreases the activation energy by ~40meV.
Conclusion
We measured the effect of tensile and compressive stressrd on floating-gate and nitride-based NVM cells using four-point mechanical wafer bending. Compressive stress degrades and tensile stress improves the retention time. Historically, process-induced stress in NVM cells has been eliminated due to deleterious effects, yet tensile stress is desirable. Recently, there have been several techniques to introduce tensile stress in logic technologies, which can also be used in NVM [8].
Acknowledgments
The authors would like to thank F. Moghadam, the senior VP of the Thin Films Group, Applied Materials, for his continuous support of this program.
References
- S.E. Thompson et al., “Key Differences for Process-induced Uniaxial vs. Substrate-induced Biaxial-stressed Si and Ge channel MOSFETs,” in IEDM Tech. Dig., pp. 221-224, 2004.
- H.S. Yang et al., “Dual Stress Liner for High-performance Sub-45nm Gate-length SOI CMOS Manufacturing,” in IEDM Tech. Dig., pp. 1075-1078, 2004.
- P. Bai et al., “A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57μm2 SRAM cell,” in IEDM Tech. Dig., pp. 657-660, 2004.
- R. Arghavani et al., “Stress Management in Sub-90nm Transistor Architecture,” IEEE Trans. Electron Devices, Vol. 51, No. 10, pp. 1740-1744, Oct. 2004.
- A. Hamada, E. Takeda, “Hot-electron Trapping Activation Energy in PMOSFETs under Mechanical Stress,” IEEE Electron Device Lett., Vol. 15, No. 1, pp. 31-32, Jan. 1994.
- Y.M. Park, J.S. Lee, M. Kim, M.K. Choi, T.K. Kim, J.I. Han, et al., “The Mechanical Stress Effects on Data Retention Reliability of NOR Flash Memory,” in IEDM Tech Digest, pp. 711-715, 2001.
- S.T. Smith, Flexures: Elements of Elastic Mechanisms, CRC Press.
- A. Al-Bayati et al., “Stress-tunable Films Enhance Transistor Speed,” SEMICONDUCTOR FABTECH, 26th Edition, pp. 84-88, 2005.
Reza Arghavani graduated from the U. of California at Los Angeles with a PhD in physics. He is a Fellow at Applied Materials, currently focused on developing thin-film technologies to enable the sub-45/73nm node logic/nonvolatile memories technology. Applied Materials, 3050 Bowers Ave., Santa Clara, CA, 95054, United States; ph 408/986-7328, e-mail [email protected].
Hichem M’Saad received his BS in metallurgical engineering at the Colorado School of Mines, his MS in materials science and engineering at Cornell U., and his PhD in materials science at MIT. He is the corporate VP and GM of Applied’s Blanket Dielectric Films Division.
Ellie Yieh earned her BS in chemical engineering from the U. of California at Berkeley. She is the VP and GM of Applied’s Gap Fill Division. She is responsible for high-density plasma and subatmospheric CVD products for all gap-fill applications.
Zoran Krivokapicreceived his MSc in solid-state physics and his doctorate degree in electrical engineering from the U. of Ljubljana, Slovenia. He is a senior member of the technical staff with Applied’s Strategic Technology Group working on emerging memory devices.
S.E. Thompson is an associate professor with the electrical and computer engineering department at the University of Florida. His current research interests are advanced transistors. Thompson has published 60 papers and holds 12 patents.