Improved yield through comprehensive CDM ESD failure analysis

05/01/2007

In semiconductor manufacturing, damage and yield losses attributed to the effects of static charges are well documented, as are the specific causes of static charge generation. [1-20]. Because charged wafers, reticles, cassettes, and other items attract more particles to their surfaces than their noncharged counterparts, particle contamination caused by static charge generation is a major yield detractor.

Furthermore, when static charge has built up on a surface and that surface comes into contact with a conductor, the static charge is “driven,” i.e., discharged, to the conductor. The direct electrical damage caused by such electrostatic discharge (ESD) to wafers, chips, and reticles [11, 15] can be modeled in a variety of modes, including human-body model (HBM), charged-device model (CDM), field-induced model (FIM), and machine-model (MM) failure modes. In addition, ESD events produce electromagnetic interference (EMI) that can cause equipment malfunctions, lockups, and direct damage to product via radiated and conducted forms [3, 10, 16].

CDM ESD damage

The focus of this article is to address CDM ESD damage to wafers and chips. In addition to providing a description of the process steps we have found to be most responsible for this type of damage, and an analysis of how the damage occurred, we also present a summary of documented yield improvements (across 12 facilities over 10 years from 1996-2006) that were realized when these failure modes were eliminated.

Wafer fixtures. Substantial CDM risks to devices on wafers can exist in most all of the operations where wafers are placed upon fixtures that are inherently high in charge generation. The wafer can become charged by induction and/or by triboelectric means (friction) while on these fixtures. In either case, subsequent contact with the charged wafer by a large conductor can discharge the devices on the wafer, causing damage in the classic CDM failure mode. A review of some of the most common scenarios is given here.

Insulative chuck materials such as Teflon (with which wafers are held in place for various operations and which are implicated in charge induction) are common to semiconductor processes. They can be found on all types of standard equipment for wafer handling. In addition, custom wafer handling and positioning fixtures can be found throughout most typical facilities. The CDM ESD risk exists with any of these chucks or fixtures when the wafer becomes charged on them and receives a subsequent discharge from a conductor.

The most common discharge mechanisms include contact by operating personnel, robot arms, and even fluids. As an example, photoresist applications surprisingly have been verified to cause CDM ESD damage in a number of our case studies. Specifically, wafers are placed typically onto Teflon chucks at the beginning of the photoresist application process. These chucks are usually highly charged; 10kV is typical if ionization is not utilized to remove the charging. The wafer, in turn, becomes charged inductively, and if it slides on the Teflon chuck, it can charge triboelectrically as well. The wafer can then be discharged by the photoresist application. The prevention technique in all these applications is quite similar: Ensure that there is no charge on the wafer at all stages before allowing contact with a material that can discharge it dangerously.

Chambers. Certain chambers, such as those found in typical plasma clean equipment, are constructed with high charge-generating, insulative materials. These chambers can create enormous electrostatic charge that can couple into open products entering the chamber. Wafer contact in the presence of that field is hazardous and can cause CDM/FIM damage.

Conveyor transport. All types of ESD-sensitive product-wafers, chips, substrates, components, and printed circuit board systems (PCB)-can become highly charged on improperly designed conveyor transport systems (via friction). It is important to verify that product charging does not occur in these conveyor systems; otherwise, CDM damage is possible whenever the product next contacts a conductor.

Although it is tempting to try using a convenient method-a static field meter-to confirm that there is no charge on the product, most often the charge level will be “unreadable” (i.e., the meter reading will appear to be zero) using the noncontacting field meter technique because the field lines from the product are terminated in the nearby metal in typical conveyor systems. However, the charge can still be present, and CDM damage can occur down the line. An effective technique [3] is to remove the product from the conveyor-via insulative tweezers so that it is not discharged-and drop the product into a Faraday Cup to read the charge, which can then be converted to voltage if the capacitance is known (Q = CV).

Dry boxes. Dry boxes can be constructed from high charge-generating plastic walls and doors. Added to the sheer size of these charge-generating surfaces, nitrogen is normally pumped into the units to maintain a dry environment. These factors combine to create a tremendous charge-generation capability, and an ESDS product that is not shielded inside will become charged via induction. Subsequent contact by operators, even if they are properly grounded, can result in CDM failure modes. A number of vendors produce ESD-safe versions of dry boxes that feature non charge-generating, static-dissipative walls and doors, with grounding for all sections.

Microscope and equipment stages. Wafers and chips are frequently inspected under microscopes (Fig. 1) and other various forms of equipment at many stages of semiconductor manufacturing. Unfortunately, many of the stages where the wafers and chips are placed are very high in charge generation. Stages made from glass or ceramic or plastics are prone to generate dangerous static fields and also cause substantial triboelectric charging when the wafers/chips slide around on that surface. If the stage is high in charge generation, an ionizer is recommended if the material cannot be changed to an ESD-safe alternative.

Figure 1. Microscope and equipment stages.Click here to enlarge image

We have observed some extraordinarily high charging levels associated with mirrors on microscope stages and have measured a few at >25kV (using simple field-meter checks). In one facility, the inspection stations made use of small (2-inch dia.) highly charged circular mirrors on top of the microscope stages to view the undersides of the tiny chips being produced. The operators would put scores of chips onto these circular mirrors at once.

Figure 2. Wet-etch operations.Click here to enlarge image

Wet-etch operations. Surprising amounts of documented device damage have been traced to wet-etch operations (Fig. 2). Wafers are placed into cassettes/baskets with handles, typically, and a series of manual or automatic dipping operations take place. Wafers become charged in these containers and then commonly are discharged by the fluids in the baths. Air blow-off is usually also part of the processes, and we have observed increased charging on occasion due to this function. It is interesting to note that the charge on the cassettes often does not diminish significantly when they are dipped into the chemicals or DI water as part of the wet-etch operations. The conductive wafers, on the other hand, usually do discharge upon contact with the fluids in many of the dipping segments of the operation. This means that the wafers can charge again (inductively) when removed from the wet-etch fluids, only to discharge again during the next dip into the next bath. Repeated charging and discharging of the wafers can occur in this manner [20]. The wafers in their carriers with handles should be bathed in ionized air at all times when they are out of the fluids in the process.

In addition, we have traced wafer damage to the bad practice of setting wafers down upon the high charge-generating sink surfaces that are typical in wet-etch units. These insulative surfaces can (and usually do) charge to 20-30kV with simple contact from operators, containers, etc., setting up dangerous fields around unprotected wafers and chips. To be safe, these surfaces should be ionized continually to remove this field-generating mechanism.

Spin rinse. Spin-rinse operations (Fig. 3) are part of every semiconductor manufacturing facility and the risks in this step are severe and typically include the following: First, if the wafer containers are charged from handling-which they almost always are right before they enter the machine-the wafers will be charged inductively. The charged wafers then become discharged; typically, the instant the first water rinse makes contact. When the spin operation ends, the wafers and the wafer container have dramatically re-charged to levels that seem to be typically the highest of any operation in the processes (20-25kV is routine). Care must be taken here to remove that charge before the next operation that will discharge the wafers.

Figure 3. Spin rinseClick here to enlarge image

Ion deposition. Ion deposition processes-or any other process that involves an inherent charging mechanism-have been the source of proven CDM damage. We have traced a number of yield loss problems conclusively to the ion deposition process itself. In these cases, chips were mounted into grounded metal fixtures inside the deposition chamber. However, the bottom of the chip consisted of an insulative layer that caused the circuitry on the chip to be electrically floating. During the ion deposition process, certain circuit areas of the chip would charge at a different rate than others (usually because some regions were essentially covered by the fixture) and internal arcs on the chip would occur between the areas of different charge (from one circuit to another). In these situations, the chip damage occurred completely as a consequence of the deposition process itself and usually resulted in damaged devices/structures in a general location on the chips.

Molding/encapsulation. We have verified substantial damage coming from the charging mechanisms associated with the molding or encapsulation processes. Typical encapsulation materials are insulative, and they become highly charged when handled or rubbed by operators, potentially leading to CDM risks. However, we have found that the greatest amount of documented damage by far has its source right where the encapsulation material is deposited onto the component or integrated circuit. Invariably, after the cooling process, a substantial charge remains on that molded part. In cases where many parts on a PCB assembly are encapsulated at one time, the total charging mechanism becomes greater and even more of a potential CDM risk at the time of a subsequent discharge.

Our experience has shown that the charging on the encapsulated parts most times remains on the parts. This can cause inductive coupling into the circuitry on the board from the output of the encapsulation process through all of the remaining process steps (which can be a substantial number), even to the packaging of the finished devices. Literally, the charging mechanism can exist at all of the remaining operations due to that initial charging at encapsulation. Ionization at the output of the machine is usually all that is needed to remove this risk from the rest of the operations.

Click here to enlarge image

Testing operations. We have found CDM damage modes at various testing operations. The most documented damage has come from burn-in board fixtures. Wafer probe operations can also present a risk but to a much lesser extent. Both operations are reviewed below.

Test sockets-burn-in board fixtures: Test sockets and burn-in board fixtures are commonplace throughout typical test operations on devices at the component level. There are two separate possible CDM failure modes that have been verified to cause device damage. First, many of these sockets, and especially high temperature sockets, charge dramatically when handled by operators, especially when they are wearing hand coverings.

There seems to be a misconception that if operators are wearing pink antistatic or black conductive gloves or finger cots (which usually do not charge significantly when rubbed against themselves), then the object that they touch or rub (the socket in this case) will not become charged. In fact, wearing those “ESD-safe” hand coverings usually causes sockets to charge 10-20 times more than what is observed after the same handling with bare hands. The resulting charging from “ESD safe” hand coverings can be identical to the values observed with regular, high charge-generating Latex gloves.

When the sockets become charged, their relatively large surface area can produce fields that can cause inductive charging of the parts about to be inserted into them. The charged part can then be discharged upon contact with the socket pins. Literally, we have observed damage occurring just by placing parts to be tested into their test sockets.

The second potential failure mode occurs if the sockets becomes highly charged. The resulting fields can cause charging of the PCB wiring on the test or burn-in board. A discharge can then take place from the board to the device as it enters the socket. This second potential damage mode is actually a mini MM failure mode as was discussed in the earlier conveyor transport section. Bathing the sockets continually in ionized air during loading and unloading of the devices eliminates both failure modes.

Wafer probes: We have experienced CDM failures at typical wafer probe operations most often when the wafers are still on their ringed adhesive tape assemblies. The devices on those assemblies become charged in all sorts of ways and device damage is likely when discharges subsequently occur. In the wafer probe operation, the wafer/chips are most often discharged when they contact the chuck underneath the probes, although discharging to the probes is a possibility in certain cases where the wafer/chips do not become discharged by the chuck

Tape and reel construction operations. CDM failures have been determined in various tape and reel operations. In almost all cases, we traced the damage to the presence of high charge-generating rollers in the process, near the devices in the tape. Metal rollers were not typically charge-generation sources, but when coated with plastic or rubber, they generated a tremendous amount of charge.

Specifically, when high charge-generating rollers slide across the plastic or ceramic package of an ESD-sensitive device, the device can become charged triboelectrically. In addition, the fields from the roller can inductively couple into the devices nearby. Any subsequent discharge is hazardous, including the conductive tape material that can normally contact the pins of the device in this operation. To be safe, all charging from any rollers in this application should be eliminated either by changing the roller material or via ionization.

Yield improvement case studies

The table includes yield improvement results from 12 companies with whom we jointly conducted yield improvement studies. Due to nondisclosure agreements, we are not at liberty to publish the names, but all were Fortune 500-type organizations. The data was collected from 1994 to 2006; however, the majority is from 2002 to 2006. In each of the studies, a baseline ESD risk analysis was performed to identify all the CDM charging and discharging risks throughout both the frontend and backend of the companies’ semiconductor process lines. Each risk was eliminated. And as the problems
isks were mostly all CDM failure modes, they were most easily addressed via ionization,

In these studies, yield improvements were realized in all cases. In some cases, only frontend (wafer-level) implementations were accomplished. We have seen enormous damage at the wafer level that has been dependent on the wafer technology and specific design. The table also notes additional information regarding where ionizer implementations were accomplished: in the frontend, backend, or both (see the entry for Facility 1), such that the CDM risks at a given facility were eliminated. Most of the yield improvement values (in the right column) were determined only after years of study.

Substantial amounts of charged device model ESD damage are not only possible, but are probable in semiconductor process line operations if the necessary ESD controls are not in place. Yield losses due to CDM electrical damage in both the frontend and backend (especially at the wafer-level process steps) are reported where such charging issues exist. Eliminating these risks is critical for state-of-the-art reliability and profitable operations.

Conclusion

Our findings on common processes that cause wafer/chip charging, which can lead to CDM failures, were presented. Yield improvement data across a number of companies over a 12-year timeframe was also presented to illustrate the elimination of select CDM failure modes.

Acknowledgment

Teflon is a trademark of Dupont.

References

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Roger J. Peirce received his BSEE from Fairleigh Dickinson U. He is currently director of technical services for Simco Ionization for Electronics Manufacture, an ITW Company, 2257 North Penn Road, Hatfield, PA 19440; ph 215/997-3430, e-mail [email protected].