Single-wafer process for improved metal contact hole cleaning
05/01/2007
Wafer cleaning is becoming an increasingly critical process module in the semiconductor manufacturing flow. As the requirements for integration precision grow, so too do the needs for cleaner and more uniform device structures. The effectiveness of cleans ultimately influences device performance and yield [1-4]. All aspects of cleans processing are being increasingly scrutinized whether in frontend or backend-of-line (BEOL) processing. One area of concern is post-etch and ash residue removal from the sidewalls and bottoms of metal contact holes prior to metallization. An incomplete contact clean is a major concern as it can lead to costly device failures.
In flash memory, metal contacts are the electrodes that connect the bit lines and active areas of the device. These connections are formed by a sequence of dry reactive-ion etching (RIE) through a resist film and the interlayer dielectric (ILD), creating a hole that is subsequently filled with metal. After the ILD etch step, the remaining resist is stripped by plasma ashing. A wet process is then required to remove polymeric residues that are left as artifacts of the dry-strip process.
As semiconductor devices shrink in size and contact holes get narrower and deeper, it is essential yet more difficult to remove the residues, native oxides, and defects from the bottoms of the contact holes as well as from the wafer surface. Otherwise, the gap fill of the upper metal electrode will be unstable, resulting in both performance and functional yield losses.
Flow defects
Wet benches have been the primary tools used for BEOL cleaning steps, including post-etch contact cleans. For device geometries greater than 180nm, conventional wet bench (batch) cleaning has been moderately effective at removing polymer residues and native oxides. However, with the development of smaller device nodes, the inherent cross-contamination associated with processing a batch of wafers immersed in a liquid becomes a greater problem. It is possible to have migration and transfer of defects from various sources and locations to the active area of a wafer. Sometimes this can be from the wafer backside or bevel to the wafer front side, but it can also be from neighboring wafers in the batch. The effects of particle migration during wet bench processing can be seen after different cleaning steps including those for pre-metallization.
 Figure 1. Representative process flow for contact hole formation and metal deposition in flash memory manufacturing |
Figure 1 shows an overview of the integration process for contact formation and metallization. The metal contact hole is formed by an RIE process through a deposited ILD, which is typically an oxide. After the various clean steps to remove resist and etch polymers, a thin barrier layer of titanium/titanium nitride (Ti/TiN) is deposited to prevent diffusion of the contact metal into the ILD. Finally, the contact is filled with tungsten, and the surface is planarized using chemical-mechanical planarization (CMP). Incomplete cleaning of post-contact holes can induce device failure, due to poor gap filling, line thinning, or delamination.
There are two general approaches possible for post-etch contact cleans. Typically, a batch of wafers is immersed into a wet bench with an appropriate solvent. The chemistry is then drained, and the wafers are rinsed with de-ionized water (DI) before drying. The alternate cleaning approach involves processing a wafer in a (nonimmersion) single-wafer tool. In this case, the process takes place in a multilevel process chamber. The chemistry is dispensed onto the top wafer surface or simultaneously onto both wafer surfaces at one level. Then, the wafer is moved to another process level where it is rinsed with DI and dried. This approach isolates the wafer frontside and backside, eliminating cross-contamination between wafer surfaces. In the case of the wet bench, the fluid dynamics of the liquid during the rinse process gives rise to a characteristic defect flow pattern that is clearly visible under defect analysis. This is absent in a single-wafer clean.
 Figure 2. Defect maps for wafers processed in a) final rinse dry (FRD) and b) DIP type wet bench processes compared to wafers processed in c) a single-wafer tool. |
To test the hypothesis that the defect flow pattern is a function of tank fluid dynamics, a comparison of the defect analysis results of two different wet-bench rinse approaches were compared with an analogous post-contact etch clean performed in a single-wafer tool, in this case a SEZ single-wafer spin processor. The corresponding defect maps are shown in Fig. 2. The image on the left shows the results for a wet-bench process, in which all process steps-chemical etch with hydrofluoric acid (HF), rinse with DI, and dry-are performed in the same process bath (known as a final rinse-dry or FRD). There is a clear, vertically oriented defect pattern visible. It appears to correlate with the flow of the DI as it circulates up and overflows the side of the bath, which may be one mechanism explaining the observations.
If, on the other hand, a wafer is processed in two separate baths-HF exposure in one bath and DI rinse/drying in another bath (DIP)-a different characteristic defect pattern is observed and shown in the center image (Fig. 2b). The cause of this pattern may be related to the flow of the defects from the edge of the wafer to the center as the wafer is extracted from the bath between process steps. In this case, the vast majority of the defects appears to be at the wafer’s edge. Further, it appears that the particles cannot be easily removed by the rinse methods used in a wet bench.
When a single-wafer process is used for the same post-etch residue clean, there in no signature defect pattern. Instead, the defectivity is random (Fig. 2c) and the overall defect density is significantly reduced relative to the batch processes.
 Figure 3. SEM and EDS data of typical flow defect observed after post-etch residue clean in a wet bench. |
While the exact mechanisms for defect migration are not completely clear, there is strong collaborative evidence from scanning electron microscopy (SEM) coupled with energy dispersive spectroscopy (EDS) that the source is the wafer edge (Fig. 3). The defects are seen in the active areas of the wafer, and they often cover contact holes and thus interfere with the filling of these features. Analysis of these defects by EDS reveals the presence of silicon, tungsten, and oxygen; these are the typical elements observed in all defect cases.
 Figure 4. Visual microscopy image and EDS data of the wafer edge prior to post-etch residue clean. |
With this fingerprint identified, a complete review was undertaken of a typical wafer prior to post-etch residue cleaning. Figure 4 shows the edge and edge-exclusion regions of a wafer examined by SEM, with an area of defectivity associated with delamination and disruption of the film stack apparent. EDS analysis confirms the presence of silicon, tungsten, oxygen, nitrogen, and titanium. The origin of these elements is the film stack used in the integration scheme. The tungsten comes from an earlier metallization process, as does the titanium. Given the elemental identification, it is consistent to hypothesize that the flow defects originate near the wafer edge and transfer via one or both of the mechanisms proposed above to the device area of the wafer. Irrespective of the transfer pathway, wet benches have significantly more sources of defects and opportunities for transfer than the single-wafer approach.
The flow defects can give rise to three issues that result in device failure and yield loss: line thinning, line delamination, and incomplete gap-fill. In order to diminish these issues using a wet bench, it is necessary to use long process times that decrease throughput and risk problems of over-etch. Thus, we implemented a single-wafer clean to eliminate these risk factors.
To optimize the overall cleaning process with respect to defectivity and uniformity, a series of tests were done to optimize the individual parameters of the clean using design-of-experiment (DOE) methods. There appears to be the strongest correlation between the defect count and the pressure in the overhead fan-filter unit flow, and a similar relationship with the exhaust pressure. The largest single factor that influences uniformity is the HF concentration. With this combined knowledge of sensitivity to operating parameters, an optimum recipe was created.
Single-wafer performance
Since a single-wafer spin processor rinses from the wafer center to the edge, there are fewer inherent defectivity transfer pathways. As shown in Fig. 2, the single-wafer approach reduces the total number of defects by up to a factor of 24.
 Figure 5. TEM images comparing metal contact holes cleaned in a wet bench and in a single-wafer tool, showing no noticeable difference in the critical dimensions. |
To monitor the performance and stability of the single-wafer process, electrical and defect data were collected for a 12-month period in production. Critical dimension (CD) variances were measured using transmission electron microscopy (TEM) as a metric of structural change between the batch and single-wafer approaches (Fig. 5). There is no noticeable difference between the CD measurements of the two approaches. Metal contact resistance measurements for both the active area and gate structures were found to be similar for batch and single wafer. However, in both cases, the variance is less with the single-wafer approach.
 Figure 6. Defectivity and yield comparisons for wet bench vs. single-wafer cleans approaches. |
Defectivity measurements gathered during the trial period for both process approaches show a significant reduction in total defects, which can ultimately lead to yield improvements. Figure 6 highlights the defectivity reduction and corresponding significant increase in prime die (device) yield. There is a clear yield improvement when post-etch residue cleaning is performed in a single-wafer cleaning tool over wafer cleaning in a wet bench.
Conclusion
We have implemented a 300mm single-wafer metal contact hole post-etch clean to eliminate a defectivity issue inherent to wet bench cleaning tools. The flow defect issue manifests itself in a characteristic pattern that appears to move defects from the wafer edge to the wafer center in a wet bench. The net effect is damage to the bit line in the form of line thinning, line delamination, and poor gap fill.
The single-wafer spin processor approach eliminates the flow defect pattern and resolves these damage concerns. Furthermore, it enables a significant reduction in the total number of defects observed and a corresponding increase in die yield without loss of device performance.
Acknowledgement
The authors would like to thank Tae Gyun Kim, Hee Kang Cho, and Bong Ho Moon for their invaluable help in the development of the data and creation of this document.
References
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Jae Yong Park received his bachelors in materials engineering from Inha U., Incheon, South Korea. He is an engineer with Samsung Electronics’ Clean & CMP Technology Group no. 12. In 2003, he joined the semiconductor business of Samsung Electronics Co. Ltd., Semiconductor Business, Memory Division, C&C 4, Hwaung City, Gyeonggi-Do, 449-711, Korea; ph 82/31-208-2273, e-mail [email protected].
Han-Mil Kim received his bachelors in chemistry from Korea U., Seoul, South Korea. He is a senior engineer in charge of Samsung Electronics’ Clean & CMP Technology Group no. 12. He joined Samsung Electronics’ semiconductor business in 1996.
Jong Kook Song received his bachelors in inorganic materials engineering and his masters in materials engineering from Hanyang U., Seoul, South Korea. He is a principal engineer in charge of Samsung Electronics’ Clean & CMP Technology Group no. 13. He joined Samsung Electronics’ semiconductor business in 1991.
Won-Ho Cho received his bachelors in chemical engineering from Hanyang U., Seoul, South Korea. He is an engineer with Samsung Electronics’ Clean & CMP Technology Group no. 12. He joined Samsung Electronics’ semiconductor business in 2003.
Eun-Su Rho received his degree in electrocommunications from Changshin College, Masan, South Korea. He worked in process applications for SEZ Korea Ltd. for 12 years.
Leo Archer received his BS in chemistry and PhD in inorganic chemistry from the U. of New Mexico, Albuquerque, NM, United States. He is SEZ’s VP of emerging technologies worldwide. Archer joined SEZ America in 1999 as a lead process engineer.