Double, double, toil and trouble!
04/01/2007
Progress in water immersion exposure technology since last year’s SPIE Advanced Lithography Symposium has been so convincing that its insertion into manufacturing at the 55nm and 45nm generations (as reported by Toshiba, STMicroelectronics, and others) is not likely to be interrupted. However, the consensus is that some evolutionary step has to be taken to extend immersion technology and keep up with Moore’s law-and at this year’s SPIE (Feb. 25-March 2), double patterning technology (DPT) seemed to emerge as the next most viable patterning method that will take us to 32nm.
There are at least four distinct near-term options for double-patterning lithography, which is distinct from “double exposure.” In double exposure (widely used with alternating phase-shifting masks), two images from two distinct masks are printed into the same resist layer, which is subsequently developed and etched into the substrate. The laws of optics forbid such methods from decreasing the pitch of patterns exposed in conventional resist, although undesirable features of the image can be cut out. While proposals have been made for unconventional resist materials that might overcome the “single-photon response” limit, none has yet appeared. Thus, higher resolution through double-patterning technology requires sequential exposure and development of different resist films and multiple etch steps to transfer the resist patterns into the substrate.
Two of the four double-patterning options interdigitate and stitch together optical exposures to form a final circuit. They differ in the tone of the process, with the most common option employing positive resist, thus making the line CDs independent of overlay, and the other making the space CDs independent of overlay, generally by employing negative resist. (Maaike Op de Beeck of IMEC showed an elegant negative-tone DPT process that used positive resist and resolution enhancement lithography assisted by chemical shrink (RELACS) post-processing to print 50nm 1:1 trenches for metal layers.) Both methods employ large pitch patterns with low duty factors, and overlay images to place a narrow feature of the later exposure in the center of the wide feature of an earlier one.
Since overlay error becomes CD nonuniformity in this kind of DPT, overlay precision and metrology are key enablers. Bill Arnold, chief scientist of ASML, reviewed the status and challenges in his keynote address to the Metrology, Inspection, and Process Control Conference. He reported that IMEC had achieved 32nm line-space patterning with the positive-tone process, using a 0.85NA exposure tool-with a k1 factor of 0.14, well below the 0.25 single-exposure limit. Jan Mulkins and Jos de Klerk, both of ASML, separately reported experiments that achieved 3nm overlay precision on a single-wafer stage of the Twinscan system, just barely enough to proceed toward 10% CDU at 32nm.
 Above - Self-aligned 32nm line-space pattern in Applied Materials APF amorphous carbon, resulting from "spacer"-type double patterning process Below. |
The other two double-patterning options avoid the worst overlay problems through self alignment, but require more complex processing. In these “spacer” processes, the first optical-exposure pattern is etched into a sacrificial layer. Another material is then deposited conformally on the sides of this spacer to a thickness that defines the final pattern. In positive-tone spacer processes, the first sacrificial layer is removed and the pattern formed by the deposited material is etched into the final hardmask or substrate. At an invitation-only Applied Materials seminar, Xumou Xu presented a method of this type that achieves 32nm resolution using an Applied APF amorphous carbon spacer and hardmask (see figures).
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In the negative-tone spacer process, reported by Woo-Yung Jung of Hynix Semiconductor, a second hardmask material is deposited over the first added layer and then partly removed. Selective etching then takes away the first added (spacer) material (a plasma-deposited carbon polymer in Jung’s case), leaving two hardmask features-one patterned by resist and one by deposition between spacers-with half the original pitch. Jung claimed that his process was the least sensitive to errors and suitable for patterning NAND flash memory at 35nm with 0.93NA ArF exposure. In most cases, a final trim exposure would be needed to remove unwanted connections and create the final circuit.
If this all sounds difficult to do, it is. Other challenges include fracturing circuit designs into mask patterns that can be fabricated in two or three exposures, rather than four or five. That will require restricted design rules, according to Hans Stork of TI. Maskmaking procedures will have to be improved, so that related masks are made sequentially on the same machine and with the best relative overlay accuracy, according to Peter Buck of Toppan. The CDs of features created in different ways will comprise different populations that will have to be distinguished in test and metrology, and the processes will need to be tweaked accordingly. As trouble-prone as double-patterning technology sounds, it does appear inevitable for the near future unless EUV or some other new technology emerges in time. -M.D.L.
Modeling becomes key to advanced and double-patterned lithography
The prominence of a dedicated joint session and a panel discussion on “computational lithography” at this year’s SPIE Advanced Lithography Symposium-not to mention the recent quarter-billion-dollar purchase of Brion by ASML-illustrate the growing importance of resolution enhancement tricks that have made it possible to approach the 45nm node using an exposure wavelength four times larger. Making sure that those tricks actually work before fabricating complex masks has become crucial. Ambitious players are emerging in this new field, with varying amounts of traction, insight, and chutzpah.
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Invarium Inc., founded in 2003, has been working to refine the many modules of its forward simulation model of the lithography process, and now claims better accuracy than anyone in predicting final resist patterns. To improve model accuracy further, they have attracted industry guru Chris Mack, one of the pioneers of predictive simulation. “I always thought my algorithms would work better than what they use for OPC,” Mack told SST in a phone interview. “Now we will find out if I am right.”
The current accuracy of Invarium models through the process window seems quite impressive, but modeling is only as good as the processs characterization. Much of Invarium’s core IP is in the parameterization area. CEO Roy Prasad reported having two paying customers for Invarium’s OPC outsource services, and a plan to provide and support software to be run in house by future large customers.
However, the challenge is about to get much harder, as pointed out by Invarium CTO Apo Sezginer and Wolf Staud, director of marketing. The problem is double patterning, where the CD process window lives in a 9+ dimensional space and the overlay specs have to be many times better than current hardware technology. “Even with unreasonably optimistic assumptions, a ±10% (full range) CD uniformity is not reasonable for [double-patterning] spaces at 40nm half-pitch,” remarked Sezginer. Statistical analysis is less depressing, though. With 3nm of overlay and 60nm of defocus, it is possible to have a 4.5nm (3σ) for spaces, if errors add in quadrature. Getting the etch uniformity tight enough will require model-based proximity correction for the etch process, according to Sezginer.
Other difficulties include BARC behavior in double patterning, which must not obscure alignment marks but also must prevent reflections from the first pattern when the second is printed. That issue is being addressed by Invarium in collaboration with IMEC, according to Staud. Also, “stubs” that connect circuits printed on different exposures can affect the linewidths of features printed in the same exposure, even though those features are one full pitch unit away in the circuit. Gates and other critical circuit elements have to avoid these “stub” regions, according to Sezginer (see figure on p. 24). Some patterns with triangular symmetry cannot be divided in half successfully.
Meanwhile, Luminescent Technologies, a venture capital-backed company started in 2002, is touting the full-chip results its customers have been getting for 45nm and 32nm contact layer patterns (140nm pitch and 110nm−100nm pitch, respectively) using the company’s “inverse lithography technology” (ILT). This system samples the desired image on a grid (as does Brion) and then “inverts” the pattern mathematically using the patented “level-set” method of Luminescent founder Stan Osher to produce an ideal “gray-scale” mask pattern. It then creates an approximation to the ideal case that can be fabricated in current mask technology.
The result is claimed to be the fabricatable mask pattern that best projects the desired image. Serifs, assist features (if needed), and the printing features are all optimized simultaneously by the “Luminizer” system, without the need for script-writing, according to company CEO David Fried, in an interview with SST. Side-lobe printing even at the edge of process windows is automatically avoided. The net result is a larger DOF than can be obtained by other OPC systems, he said.
Computation is done on hardware supplied by Luminescent that “soon” will include dedicated accelerator cards using FPGA technology (like Brion’s), according to Director of Engineering Bob Gleason-but even without acceleration, the ILT system runs as fast at 65nm as conventional “edge-placement” OPC, he reported. The scaling laws are such that it will run faster at 45nm, he claims. For 45nm contact and poly layers, mask writing takes <8 hours for a full chip, less than reported for conventional OPC by Luminescent’s customers. The mask worked better, too, with 100nm more depth of focus, according to Leo Pang, VP of marketing. -M.D.L.
HP’s crossbars pay off three nodes early
In early January in Palo Alto, CA, SST editors got a peek at Hewlett-Packard’s “crossbar array” technology-once considered for far future memory and logic, but now viewed as a new 15nm-width field-programmable nanowire interconnect (FPNI) circuit that may see production in 2010 along with 45nm process technology, three nodes earlier than anyone expected. This novel circuit architecture appears to be both manufacturable and scalable, with what seem to be only two new unit processes: nanoimprint lithography (NIL) for the bar formation, and the spin-on/etch of the molecular switching layer. Modeling of FPNI circuits show functionality with scaling down to 4.5nm-wide crossbars.
 Figure 1. Nano crossbar array (2x2) schematic showing the switching material patterned by the top electrodes. |
One of the noteworthy aspects of the crossbar design is that none of the manufacturing control has to be perfect-bars are expected to fail, and signal multiplexing through redundant lines compensates. Prior reports had indicated that 11 lines of a generic crossbar array could have 10% random failure and still guarantee 100% signal transmission of an eight bit-wide multiplexed data stream. For FPNI circuit applications, HP’s models show that a crossbar array with 20% randomly failing lines should still provide 75% chip yield.
The bottom electrode is platinum, while the top electrode is platinum over titanium (see Fig. 1). Forming the cross connections between the orthogonally aligned top and bottom bars are molecular monolayers. The monolayer is blanket deposited over the patterned bottom electrodes, and then etched using the top electrodes as the mask. Each cross-junction is a resistive memory element within an array that can function as a memory or latched-logic circuit, or an FPNI.
Both electrodes are formed by lift-off lithography using dual-layer resist (Fig. 2). “People do not know how to do platinum etch,” reminded HP scientist Wei Wu, team member along with Shih-Yuan Wang and Philip J. Kuekes. “So we have to do a lift-off process.” The top “imaging layer” of resist is formed by NIL-HP built its own NIL tool, and is currently working on the 5th generation. E-beam direct writing with 60nm pitch is used for NIL mold fabrication, but some tricks allow doubling of the spatial frequency along with dual e-beam writing so that they can achieve 30nm pitch today. Then the bottom “transfer layer” resist is formed and undercut by sequential isotropic and anisotropic RIE. The undercut is essential so that the sidewalls are not coated by metal PVD, which allows for clean lift-off of the metal on top of the resist when the resist is stripped. “That’s how we can get crossbars with much higher yield,” Wu said.
It’s worth noting that lift-off was a standard way to form metal interconnects back in the 1970s when linewidths were multiple microns. In all lift-off processes, the metal deposited between resist lines remains in place, while a wet solvent dissolves away the resist such that any metal on top just floats in the strip solution. This is a bit of an inherently messy situation, and stripper flow and filtering must be properly managed so that these bits of metal do not drop onto the wafer surface as defects. Still, with proper control of the resist to eliminate any sidewall deposition, lift-off patterning can be highly robust and manufacturable.
We don’t really know any of the details about the processing of the molecular monolayer, but we may suspect that its final form can sustain the temperatures used in standard packaging processes. Since the array is the top-most layer in the FPNI design, the monolayer need not be compatible with the 400°-450°C standard used in the lower interconnect processing. Working FPNI chips aren’t expected for a year, and there are certainly many details to be resolved before the anticipated 2010 manufacturing debut of nanoarrays. But the crossbar prototypes seen in the lab look good. -E.K.
New Surfscan system summons ghosts from the haze
Building on its venerable Surfscan unpatterned-wafer-inspection legacy, the new SP2XP system from KLA-Tencor Corp. is designed for the 45nm IC manufacturing requirements for all types of bare wafers. The company claims the system can detect all major types of defects of interest, and quickly group wafers into defect-free, reworkable, and scrap categories.
Sumitomo, SEH, and Soitec have already beta-tested the new system with 45nm-generation wafers. “The new Surfscan SP2XP system provides the SOI sensitivity, independent of film thickness, that we require to address 45nm chipmaking, while at the same time providing a major leap forward in productivity,” noted Christophe Maleville, VP of process engineering at Soitec.
KLA-Tencor claims that >98% of all 300mm product wafers in the industry are inspected by an SP1 or an SP2 system at least once. IC manufacturers all do some manner of incoming quality inspection on bare silicon wafers-typically 20%-100%, depending upon many factors-and the system’s output data files are in standard KLARF format.
The technology will be extended beyond bare-substrate inspection to the large number of blanket film tool-monitoring applications required in semiconductor manufacturing, such as qualification and monitor wafers, and backside inspections. “We will follow up with a release for the IC market sometime in the calendar year,” promised Rahul Bammi, KLA-Tencor’s director of marketing.
The addition of a new brightfield channel to dual-incidence darkfield channels provides five input signals, with a sixth signal provided by the noise-like intrinsic micro-roughness of the wafer surface (the SURFimage). Multichannel comparison algorithms then separate unacceptable “intrinsic” defects from re-workable ones, in a single rules-based binning (RBB) step.
The system’s UV wavelength confines the laser beam to the wafer surface, minimizing false counts from buried defects and providing 30nm sensitivity. With one order of magnitude greater SURFimage resolution, the new system can capture previously unnoticed defect types. Shallow CMP scratches, orange peel, watermarks, slurry residue, and surface roughness changes can emerge from the intrinsic background haze like ghosts from a fog.
The company says the new system delivers 20%-50% higher throughput (depending on the operating mode) compared with the SP2, even with the added detection capabilities, which translates into a lower cost-of-ownership. -E.K.
Laser annealing moves to the front burner at Ultratech
Moving beyond its pilot production efforts with logic manufacturers worldwide, Ultratech Inc. highlighted application of laser spike annealing (LSA) to DRAMs in a joint paper with Samsung at the recent IEDM conference [1]. Ultratech execs Art Zafiropoulo and Yun Wang summarized key findings for SST and offered insights on the company’s future direction for the technology.
Using LSA for a DRAM with a tungsten gate stack minimizes pattern effects when inserted into the contact process flow (i.e., BEOL), but Wang, Ultratech VP and chief technologist for laser processing, indicated the company is making efforts to demonstrate that LSA can be inserted at any point in the process-not just at the contact process-and still minimize pattern effects.
The researchers found 4% and 14% improvements in drive currents for peripheral nFET/pFET transistors, respectively, and also noted an improvement in cell transistor drive current and leakage with no reliability degradation or extra defects. The team attributed the reduction in leakage current to defect-curing by the high-temperature annealing (1350°C) and reduced depletion width by increased activation [1].
Wang maintains that the Samsung paper describes the first application of LSA to DRAMs, while all other papers are for advanced logic devices. “DRAM uses tungsten gates, which pose more complications-the cell where data is stored requires low leakage for longer data retention and lower power consumption,” he explained.
Ever since unveiling the first application of laser annealing technology in June 2003, Ultratech has been working to ready the technology for more advanced nodes. With the need for thinner gates as the industry approaches 32nm half-pitch, annealing times will have to be even faster, posing problems for flash lamp-based rapid thermal annealing and even laser diode bar technologies, explained Zafiropoulo, chairman/CEO/president. He predicts that competing technologies will not be extendible to 32nm and will also have cost-of-ownership limitations.
“DRAM is still lagging in junction formation by about one generation,” said Zafiropoulo. “That’s why we targeted logic first and in early 2006 started work on memory.” The company is currently pursuing integration of its technology into logic devices at various sites worldwide.
There’s also an interesting side note to the technology story. In 2000, at the behest of a major customer that wanted a second (and larger-supplier) source for the company’s laser annealing technology, Ultratech licensed much of its melt technology to Applied Materials Inc., which had selected the laser diode for further development. According to Zafiropoulo, Ultratech did not want to pursue melt technology for advanced nodes due to its inherent limitation: so-called stitching effects (i.e., pattern effects) that arise when square waves are used for scanning.
Asked to comment on whether or not Applied Materials will license Ultratech’s current sub-melt laser technology, Zafiropoulo said he did not know the answer, implying that there are legal issues up for debate. He did note, however, that Applied has acknowledged using the new technology for sub-melt laser annealing. -D.V.
1. G. Buh, G-H. Yon, T. Park, J-W. Lee, J. Kim, Y. Wang, et. al., “Integration of Sub-melt Laser Annealing on Metal Gate CMOS Devices for Sub-50nm Node DRAM,” IEDM Technical Digest, p. 33.4.1-33.4.4, (2006).
Clear Shape takes a stab at changing the shape of the DFM turf
The proliferation of DFM start-ups set the stage for a plethora of announcements leading up to the SPIE Microlithography Conference. Another entrant trying to alter the DFM landscape is Clear Shape Technologies, backed by several venture capital supporters (including the VC arms of Intel and KLA-Tencor), which announced two products last November:InShape and OutPerform. InShape uses a nonlinear optical transformation algorithm to detect potential manufacturing failures during physical design to predict full-chip contour shape predictions across the process window (see figure). Using output from InShape, OutPerform takes timing, and place
oute data together with encrypted fab technology files to identify timing and leakage parametric hotspots for violations due to systematic variations. The resulting timing optimization directive drives place
oute tools.
While all fabs have their own DFM kit, what Clear Shape does, according to VP of marketing and business development, Nitin Deo, is to predict during the design stage how the ideal GDS shapes will print as contours in silicon. From that, designers can predict hot spots and parameter variations. “Most of our work is in creating those models and calibrating them to a particular silicon manufacturer’s backend process,” he noted.
The company claims that full-chip prediction of silicon contours across the process window can be done within eight hours for an 18mm × 18mm chip. Deo maintains that the company’s technologies are manufacturing/OPC tool agnostic, and that the contour predictions are >90% accurate between the ideal GDS shapes and silicon, regardless of which “in-between” OPC tool might have been used.
The company has been working with TSMC, UMC, IBM, Samsung, Chartered, NEC, and others to correlate its contour predictions to a specific fab’s silicon (i.e., calibrating the models). Deo said that contour prediction calibration and hot spot detection correlation have been achieved for several customers: TSMC (65 and 55nm nodes: done, 45nm: to be released soon); IBM/Chartered/Samsung (65nm), and NEC (90nm: done; 65nm: to be completed soon). STARC recently became a customer, and Deo publicly identified ATI as one as well.
Making contour prediction the company’s mission arises from the reality that no matter what, as ideal GDS shapes go through post-GDS manipulations, contours on silicon are the end result, and they change with respect to process conditions. “Manufacturability involves predicting how those ideal GDS shapes will change into contours and how those contours will impact the chip performance,” he noted. Some of the problems encountered could result in either catastrophic failure or compromised chip performance (e.g., electrical, timing, power).
Deo also described what he calls the “variability challenge”-i.e., with each technology generation the variability in device performance increases, and the difference in variability is quite dramatic when going from 65nm to 45nm. “If you look at that 65nm and 45nm performance variation, there is overlap between the two-so if the best performance ‘corner’ of 65nm is the same as the worst performance ‘corner’ of 45nm, why would you go to 45nm?” he asked. “That means you are not getting the maximum value out of your process technology.” The answer is to control the variations, but that first requires that one can predict their causes, he said. “Then you can put some preventive measures into your design.” -D.V.