Re-enabling Moore’s Law with re-engineered gate stacks
04/01/2007
Advanced transistors: Last of three parts
After years of struggling to delay the inevitable, it is clear that a replacement for the traditional oxide/polysilicon gate stack is needed, and sooner rather than later. Yet a review of the options finds little consensus. The dielectric will be based on hafnium, but exactly which hafnium compound (or compounds)? Since polysilicon won’t work as a gate for hafnium-based dielectrics, which metal offers the most manufacturable solution? This article considers the areas of agreement and the many remaining open questions.
Silicon’s place at the center of the IC industry is due as much to the native oxide, SiO2, as to the properties of silicon itself. SiO2-chemically robust, thermally stable, and a good insulator-has performed many tasks, from insulating adjacent metal interconnects to transistor isolation. Yet its most important role has been as the gate dielectric at the heart of each metal oxide semiconductor (MOS) capacitor.
The MOS capacitor supplies the charges that flip a MOSFET to the on state. Applying a charge to the gate electrode attracts carriers of the opposite sign to the dielectric-channel interface. These minority carriers-holes in pMOS or electrons in nMOS devices-have the same sign as the source and drain doping. They invert the nominal charge distribution, effectively removing the junctions between the channel and the source and drain, and allowing current flow.
If the gate capacitance increases, the gate charge attracts more carriers into the inversion layer. The switching frequency (1/τ) of the transistor depends on the drive current (Ion), drive voltage (Vdd), and the gate capacitance (C):
To maintain or improve the switching frequency as transistors shrink, a physically smaller channel must carry the same amount of drive current. More carriers must flow through the inversion layer and so the capacitance must increase. For most of the IC industry’s history, manufacturers increased the capacitance by making the dielectric thinner. The capacitor (Cox) depends on the thickness (Tox) and permittivity (εox) of the gate dielectric:
Unfortunately, a thinner layer allows more leakage as more carriers tunnel through it. Leakage is a substantial fraction of total power consumption for both low-power and high-performance devices. It affects battery life, data center cooling costs, and any other parameter that depends on off-state current. According to U. of Florida professor Scott Thompson and researchers at Intel, devices with leakage in excess of 10-25% of total power consumption are not commercially practical [1].
Beginning with the 130nm technology node, manufacturers added nitrogen to the gate dielectric to increase the dielectric constant. SiON offers only a modest improvement over SiO2, however, and dielectric thickness continued to drop. The practical limit of a functional SiON dielectric-between 1.1 and 1.2nm-was reached by the 65nm node, effectively bringing gate scaling to a halt. The first two parts of this article considered attempts to improve performance by other means, such as the use of high-mobility channel materials (February) and strain engineering (March). Though strain engineering has been quite effective, and high-mobility channel materials have shown promising results, an improved gate dielectric is still needed.
Integrating hafnium
Replacing the nearly ideal processing characteristics of SiO2 has been enormously challenging. According to Ivo Raaijmakers, CTO at ASM International, serious high-k dielectric research began in 1997, and is only now coming to fruition. Identification of the dielectric itself was relatively simple. After briefly considering candidates such as Ta2O5, the industry consensus quickly settled on hafnium-based oxides as the most likely dielectric material. But actually integrating the new material into manufacturable transistors with the required performance specifications has been much more difficult.
One major complication arises because the simplest hafnium-based oxide, HfO2, tends to crystallize and phase segregate at the high temperatures needed for dopant activation anneals. This behavior is undesirable because the dielectric properties vary with crystal orientation and grain size. In early research, the interface between HfO2 and silicon was poor with a high density of interface traps. According to Gary Miner, CTO for the Front End Products group at Applied Materials, leading companies have learned how to create and scale good interfaces between HfO2 and other components of the gate stack.
Still, manufacturers are using a variety of optimizations to achieve the combination of properties they need. One possible optimization is the use of HfSiO, which forms a cleaner interface. It has a lower dielectric constant than HfO2, however, and is therefore less scalable to smaller device dimensions. A further modification, adding nitrogen, improves thermal stability, suppresses crystallization, and improves the dielectric constant. Proving that no perfect material exists, unfortunately, nitrogen near the channel interface degrades carrier mobility.
In practice, Miner explained, it is not so easy to distinguish among HfO2, HfSiO, and HfSiON dielectrics. Hafnium, silicon, and oxygen are present in the process chamber during any hafnium-based dielectric deposition. Formation of at least a few monolayers of SiO2 and HfSiO is inevitable. Adding some nitrogen optimizes this interfacial transition layer, minimizing its contribution to the total dielectric thickness. Rather than arguing the relative merits of HfO2, HfSiO, and HfSiON, the challenge for process engineers is to optimize a film stack that contains all three. The ultimate goal is a graded dielectric profile that achieves a high quality interface without degrading either carrier mobility or dielectric constant.
High-performance device manufacturers, Miner said, tend to insist on precise, atomic-layer control of the dielectric film stack. Because of the close relationship between capacitance and switching speed, variations in the dielectric thickness or properties can cause circuit timing variations. These manufacturers tend to prefer atomic layer deposition. ALD may also be more extensible to 3D structures such as FinFETs, though the commercial prospects for such structures remain uncertain.
Low-power devices, on the other hand, tend to use a thicker dielectric layer to minimize leakage current. These devices tend to target such high-volume, cost-constrained applications as cell phones and other personal electronics. Here, precise profile control is less important than high throughput and low cost. Many of these devices rely on MOCVD, rather than ALD.
Though most published work on advanced gate dielectrics emphasizes hafnium silicates, several groups have added other elements to the mix. According to Suresh Venkatesan, Freescale’s senior director for CMOS platform device development, his company has found that adding zirconium, making HfZrO2, improves reliability. Zirconium reacts with polysilicon, so this combination requires the use of metal gate electrodes. Elsewhere, in work reported at the IEEE Electron Device Meeting (IEDM) in December, researchers at TSMC found that HfLaON dielectrics could maintain their amorphous state at 1000°C while still having a dielectric constant of 20 [2].
Replacing polysilicon
The proliferation of dielectric compositions is due in part to the challenges posed by integration with the gate electrode. Even with high-k dielectrics poised to enter production, gate integration remains the focus of substantial research and debate.
Very early in the development of hafnium-based dielectrics, it became clear that they would require an alternative to the polysilicon gate electrode. Even with SiON gate dielectrics, polysilicon carrier depletion has become a serious problem. Polysilicon depletion occurs because the accumulation of charge near the dielectric depletes the surrounding semiconductor. A semiconductor depleted of free carriers behaves as an insulator, increasing the effective dielectric thickness. Though the depletion region is only 3-4Å thick, it accounts for a significant fraction of the total thickness when the dielectric itself is only 1.1nm (11Å) thick.Increasing the dopant concentration in the gate electrode helps. The more free carriers that exist in the material, the more that remain after the inevitable accumulation at the dielectric. Yet gate doping already approaches the saturation level, and boron penetration through the dielectric is already a problem. One solution is to use metallic electrodes, which are not vulnerable to depletion because of their abundance of free carriers.
When polysilicon electrodes are used with hafnium dielectrics, an even more serious problem appears: the transistor’s threshold voltage (Vt) shifts. In nFETs, the threshold voltage tends to be more positive by about 0.2V, while in pFETs, it is more negative by about 0.6V. The shift appears to occur because the effective work function of the polysilicon is pulled toward the center of the band gap. Changing the polysilicon work function changes the voltage at which the channel inversion layer forms. Vt control is a critical aspect of circuit optimization, and the lack of it renders polysilicon gates unusable with hafnium-based dielectrics.
Though the Vt shift is generally attributed to Fermi level pinning caused by interface states, the precise defects responsible for these states are not yet known. Proposed causes include Hf-Si bonds, oxygen vacancies, or foreign atoms of some kind. Attempts to prevent Hf-Si bond formation by adding a cap layer between the dielectric and polysilicon have had mixed results, so this theory remains unproven. Lateral diffusion of oxygen into the dielectric layer helps to reduce the Vt shift, but adding oxygen tends to encourage SiO2 formation near the channel, increasing the dielectric thickness [3].
Whatever the cause, the need for alternative gate electrodes for hafnium-based transistors has significantly delayed the introduction of these materials. Finding an entirely new gate stack is far more complex than simply replacing the dielectric.
Ideally, the work function of the gate electrode should be near the appropriate edge of the silicon band gap. In polysilicon, implanted dopants create either n-type or p-type polysilicon, as needed. For metals, in contrast, the work function is a fundamental property of the material and its interfaces. Changing the work function means changing the composition.
Yet using two completely different metals for pMOS and nMOS electrodes doubles the process complexity and more than doubles the potential interactions that must be considered. Moreover, many candidate metals are unstable at dopant activation temperatures.
Current manufacturing schemes use a self-aligned gate-first process (Fig. 1): the gate structure is created first, and the rest of the transistor aligned relative to it. The polysilicon gate protects the channel and the dielectric from aggressive etching and stripping chemistries.
If the gate can’t tolerate the dopant-activation anneals, however, a replacement-gate process must be used instead. In a replacement-gate process (Fig. 2), a sacrificial material serves as a placeholder during source and drain implant and anneal, then is etched away to make room for the permanent gate. Among other challenges, the replacement-gate scheme exposes the channel silicon to potential etching damage.
Nickel silicide
Faced with the prospect of a dual-metal replacement-gate process, manufacturers focused their integration efforts on NiSi, a familiar alloy already used for contact silicidation. NiSi forms several different compounds, depending on the relative fractions of nickel and silicon. By varying the gate composition, manufacturers can define the work function.
The NiSi approach-NiSi gates are often described by the acronym FUSI, for fully silicided-presents several problems. First, as noted previously, some research suggests that the Vt shift observed with polysilicon gates is due to Hf-Si bonds at the dielectric-gate interface. Since NiSi also contains silicon, it might not eliminate the problem. Furthermore, the work functions of the various NiSi compounds (see Figure 3) still lie generally near the silicon bandgap. Alhough NiSi allows some degree of Vt control, NiSi does not deliver the band-edge work functions that high-performance devices require. Researchers at IMEC have tuned the NiSi work function by implanting Pt (for pMOS) and Yb (for nMOS) dopants, but it isn’t yet clear whether this process will be manufacturable [5].
 Figure 3. The effective work function of nickel silicide varies with composition, from below to above the silicon midgap value. (Courtesy: NEC Corp. [4]) |
The process control needed to achieve consistent properties poses a more serious challenge. In a typical nickel silicide process flow, gate deposition, spacer formation, source and drain silicidation, and oxide passivation are the same as in a conventional polysilicon-gate CMOS process. To form NiSi gates, however, these steps are followed by CMP removal of the oxide passivation layer, exposing the polysilicon gate. Selective etchback of the polysilicon creates a well for the deposition of nickel, and the thickness of the remaining polysilicon defines the eventual NiSi ratio. This polysilicon thickness therefore defines the Vt of the transistor, a critical process parameter. Unfortunately, CMP is not known for uniformity or thickness control, and can introduce significant variability in the initial polysilicon thickness. It is not evident whether a CMP-limited process can achieve the process control required.
One possible solution, presented by researchers from IMEC at last year’s VLSI Technology Symposium, inserts a sacrificial SiGe cap layer after polysilicon deposition but before oxide passivation. This cap protects the polysilicon during CMP, then it is removed to allow for a normal polysilicon etchback process [6].
After polysilicon etchback, nickel deposition is followed by a two-step RTP process, first diffusing nickel into the silicon, then driving the silicidation reaction to completion (Fig. 3). A final etch removes any excess, unreacted nickel. Process control for these RTP steps is critical, with only a 5-10°C difference having a substantial impact on the process outcome. If the reaction time is too short, or the temperature too low, incomplete silicidation results, and the gate exhibits polysilicon-like behavior. If the reaction time is too long or the temperature too high, then excess nickel can be forced into the polysilicon, potentially even punching through the dielectric. IMEC researchers claim that the improved polysilicon thickness control achieved with a SiGe cap layer can increase the RTP process window from only 5°C to as much as 20°C.
Even with improved polysilicon thickness control and a larger RTP process window, it’s still not clear whether the NiSi process is manufacturable. Gate structures for the 45nm technology node are very small. As Applied Materials Fellow Reza Arghavani explained, it’s difficult to achieve consistent grain structure and orientation in such small areas, while even small variations in structure can affect electrical performance.
Low-power applications can tolerate the Vt variations that might result from NiSi process variability, while the reduced cost of a single metal solution is a major advantage. High-performance device manufacturers, in contrast, appear to have largely abandoned NiSi in favor of a dual-metal approach.
Dual metal
Exactly which dual-metal approach remains an open question, however. As discussed above, gate-first integration schemes require metals that can tolerate temperatures in excess of 1000°C. At these temperatures, many conductors react with the dielectric. For nMOS transistors, the industry appears to have concluded that titanium and tantalum nitrides and carbides are the most promising compounds. Ta compounds, in particular, have been mentioned in many published reports. According to Raaijmakers, processing can tune Ta performance characteristics as desired. Although Ta compounds are not band-edge metals, Raaijmakers stated, they should be “good enough” for many applications.
No such consensus yet exists for the pMOS metal. In fact, most papers in the open literature consider a wide range of alternatives, usually finding all of them wanting. As Arghavani put it, “the leading companies know what the answer is [for pMOS], but they aren’t saying.” Noble metals, such as platinum and iridium, have the desired work function and temperature tolerance, but are notoriously difficult to etch. Conductive oxides, such as iridium oxide, are unstable at high temperatures.
In metal-gate structures, as in polysilicon structures, there is a tendency for the effective work function to drift toward the middle of the band gap after anneal. Annealing in an oxidizing ambient reduces the work-function shift, again indicating oxygen vacancies in the dielectric as a possible cause [3]. Arghavani pointed out that many metal integration difficulties might actually be resolved by the use of a replacement-gate scheme. Dual-metal schemes lose many of the advantages of a gate-first structure, as the first metal must be etched away before the second metal is deposited, potentially damaging the silicon (see Fig. 1). Depositing the gate after the activation anneal helps prevent work-function shifts, and generally allows more flexible selection of the metal.
Again, no consensus appears to have formed on this point. IBM and Intel, the two companies with announced production-worthy 45nm processes, are saying very little about their integration schemes. Intel senior fellow Mark Bohr confirmed that Intel’s integration scheme uses two different band-edge metals and that the hafnium-based dielectric is deposited by ALD. Bohr would not identify either the nMOS or the pMOS metal, nor would he confirm whether the company is using a gate-first or replacement gate-integration scheme.
IBM’s director of silicon technology, Ghavam Shahidi, was only slightly more forthcoming, confirming that the company uses a gate-first integration scheme. IBM employs a dual work function process, Shahidi said, with both nMOS and pMOS devices using metals from the same alloy system. Though Shahidi provided no further details, previously published work by IBM has discussed the use of a TiN electrode with a polysilicon cap layer [7]. In nMOS devices, adding an Mg or La-based cap can shift the work function toward the band edge, offsetting the Vt shift induced by the TiN electrode. Sony, an IBM technology partner, also reports successful integration of TiN with pMOS devices.
Based on these fragmentary clues, it seems likely that the IBM and Intel processes differ from each other and from the integration schemes used by low-power manufacturers such as Freescale. While SiO2 and polysilicon were universally accepted for decades, the switch to new materials is causing fragmentation. So far, no metal/dielectric combination has proven itself as versatile as the oxide/polysilicon stack was. Until a single scheme proves it can meet the needs of all devices, consensus is likely to remain elusive.
References
- Scott E. Thompson, et. al., “In Search of ‘Forever,’ Continued Transistor Scaling One New Material at a Time,” IEEE Trans. Semi. Mfg., Vol. 18, pp. 26-36, 2005.
- C.H. Wu, et. al., “High Temperature Stable [Ir3Si-TaN]/HfLaON CMOS with Large Work-Function Difference,” IEDM Tech. Digest, paper 23.1, 2006.
- E.P. Gusev, V. Narayanan, M.M. Frank, “Advanced High-k Dielectric Stacks with PolySi and Metal Gates: Recent Progress and Current Challenges,” IBM J. Res Dev., Vol. 50, No. 4/5, 2006, http://www.research.ibm.com/journal
d/504/gusev.html. - K. Takahashi, et al., “Dual Workfunction Ni-Silicide/HfSiON Gate Stacks by Phase-controlled Full-silicidation (PC-FUSI) Technique for 45nm-Node LSTP and LOP Devices,” IEDM Tech. Digest, pp. 91-94, 2004.
- H. Y. Yu, et al., “Demonstration of a New Approach Towards 0.25V Low-Vt CMOS Using Ni-based FUSI,” VLSI Tech. Digest, pp. 98-99, 2006.
- A. Veloso, et al., “Dual Workfunction Phase-controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability and Process Window Improvement by Sacrificial SiGe Cap,” VLSI Tech. Symp., p. 94, 2006.
- V. Narayanan, et al., “Band-Edge High-Performance High-k /Metal Gate n-MOSFETs using Cap Layers Containing Group IIA and IIIB Elements with Gate-first Processing for 45nm and Beyond,” VLSI Tech. Digest, 2006.
Katherine Derbyshire is a contributing editor at Solid State Technology. She received her engineering degrees from the Massachusetts Institute of Technology and the U. of California, Santa Barbara. She is the founder of consulting firm Thin Film Manufacturing, [email protected], http://www.thinfilmmfg.com.