Maximizing power device yield with in situ trench depth measurement
04/01/2007
Many power devices rely on a silicon trench technology for operation. This article discusses the importance of trench depth control, provides examples of various trench etch applications, and evaluates a technique for in situ depth monitoring. Finally, the implications of these techniques on device yield are considered.
Power handling is a pervasive area of the semiconductor industry with power devices present in everyday products such as PCs, PDAs, automobiles, handsets, and white goods. For several types of power semiconductors, significant advantages in device performance can be achieved by the use of a silicon trench technology.
In the case of a trench MOSFET power device, the feedback capacitance, Cgd, between the gate and drain regions largely determines the device switching speed [1]. The larger Cgd becomes, the longer it takes to switch charge, and the slower the device becomes, leading to intolerable losses for devices designed to operate at high frequency. The gate polysilicon and the drain silicon form the capacitor. Theoretically, the best devices are made when the trench is narrow and extends just beyond the p-n interface.
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The ultimate trench width is governed by the photolithographic capabilities of the specific manufacturer and the compatibility with subsequent processing steps. The position of the p-n junction can be accurately controlled during ion implantation. This leaves trench depth control as the major factor involved in minimizing Cgd, and it is the most critical parameter to control during the etching of silicon trenches. Other parameters to control include the smoothness of the trench sidewall (which minimizes the gate leakage current), the sidewall profile (for successful filling with polysilicon while avoiding ‘key hole’ voids), and trench bottom rounding.
Chemistry and plasma source
Table 1 summarizes various chemistries that may be used for etching trenches in silicon. Aviza uses the SF6/O2 approach for trench etching for power devices. This approach relies on balancing etching reactions between F-atoms and the silicon substrate (to form SiFx by-products) with sidewall passivation due to the interaction of the etched silicon sidewall with oxygen in the plasma (to produce SiOy). Where required (mainly for deep structures), additional sidewall protection can be achieved by adding CF4 or SiF4 into the process gas mix.
 Figure 1. Examples of typical trenches required for production of power devices. |
Figure 1 shows a broad range of typical silicon trenches that are required for power device production. Each trench is characterized by having a smooth sidewall with a slightly tapered (~89˚ profile) and a rounded bottom section. The silicon etch rates for these processes are in the range of 2.2-3.6µm/min, delivering throughputs of 20-33wph per inductively coupled plasma (ICP) process module. Within-wafer etch rate uniformities are typically in the range ±1.0-2.5% (max-min/2x mean). Additional details regarding the key process parameters that influence the etch rate uniformity, trench bottom rounding, sidewall angle, and CD loss can be found in a separate article [7].
In situ diagnostics
Controlling the trench etch depth is more difficult than for most dry etch applications because for most power devices there is no stop layer at which etching can be terminated using conventional optical emission spectroscopy (OES). Attempting to control the depth simply by adjusting the process time is subject to many possible inconsistencies, such as variations due to chamber condition or loading effects due to mask open area changes from device to device. Typically, only ±4% depth accuracy wafer-to-wafer is achieved with timed etches, and in many cases, this level of control is insufficient for high device yield.
 Figure 2. Typical IEPD trace for 15µm deep trench. |
To meet the trench depth repeatability levels that are required for robust manufacturing, it is necessary to integrate an analytical tool onto the etch chamber that can directly measure or compute the etch depth in real time. Interferometric endpoint detection (IEPD) represents a method of depth monitoring. The technology is implemented with a ‘white’ light source, an optical tilt head assembly, and a combined wavelength selection and detection unit. The white light source emits a broadband optical signal that is transmitted via optical fibers to the optical tilt head assembly situated on a central viewport of the ICP chamber.
 Figure 3. An ~3x 70µm power trench etched using the Bosch process. |
The process gas is also introduced centrally. The tilt head assembly produces a collimated light beam normal to the wafer surface. Adjustment of the tilt head enables accurate alignment of the beam relative to the wafer. The sampling area on the wafer is typically 15mm in dia. There is no requirement to align the beam relative to the features on the wafer-IEPD effectively samples an average of etched and nonetched areas. Light reflected from the wafer is collected by the same assembly and transmitted by optical fiber to the detector, which measures the light intensity at a preselected wavelength.
A PC captures the oscillating light intensity and uses Fourier analysis to directly calculate the silicon etch rate and trench depth. The analytical units (interferometers) are commercially available (examples include the Verity SP2000 spectral reflectometer and the JY Horiba Digilem white light interferometer).
A typical output signal of optical intensity measured during the etching of a silicon trench is shown in Fig. 2. In this case, the trench is 15µm deep. The optimum wavelength that is chosen for a particular trench etch is dependent upon the intensity of the signal compared to the intensity of the plasma itself, the depth of the trench (because the reflection of longer wavelengths from the base of the trench become suppressed with depth), and the transparency of the masking layer.
Figure 2 shows two superimposed oscillation frequencies. One has a period of ~100 seconds and is due to the erosion of the mask layer (in this case, silicon dioxide) and the higher frequency response has a period of ~3 sec and is due to the etching of the silicon trench itself. The ratio of these periods reflects the etch selectivity of silicon relative to the mask, as confirmed by SEM measurement to be ~35:1.
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For much shallower trenches, differentiation and smoothing algorithms are used to assist in separating the two oscillations. A Fourier transform of the signal is used to identify the frequency of the silicon trench oscillation, which is converted into a silicon etch rate using the formula:
where Ertr is the trench etch rate in nm per minute, f is the frequency of oscillation in Hz, and λ is the wavelength in nm.
Figure 2 also shows a limitation of the IEPD approach. The interference fringes for the etching of the trench reduce in amplitude as the trench deepens. The trench bottom basically becomes less efficient at reflecting the incident light back to the detector-a situation exacerbated by the preferred rounding of the bottom section. This limits the depth to which the trench can be directly monitored to ~10µm. However, for deeper trenches it is adequate to monitor the depth for the initial 10µm and then compute the end-point time for the full process by assuming an etch time for the latter stages.
It turns out that trenches deeper than ~15µm are difficult to etch with the SF6/ O2 approach due to breakdown of the passivated sidewall near the top of the trench-this can be the case even when additional passivation gases (such as CF4) are introduced. For this reason, deep trenches for power devices are also starting to be etched using the Bosch gas-switched approach. Figure 3 is an example of etching to a depth of 70µm using this technique. Scalloping of the sidewall (a natural consequence of the Bosch approach) may be minimized by increasing the switch times and limiting the net etch rate. In any case, scalloping tends to be restricted to the upper portions of high aspect trenches like these (<5µm depth, in this case).
Trench depth repeatability
IEPD allows the silicon trench etch to be terminated at a preprogrammed depth. The process time is allowed to ‘float’ to the point at which the required depth is achieved and provides for the following: 1) automatic compensation for etch rate variations introduced by the process chamber condition; 2) automatic compensation for etch rate variations introduced by the wafer condition; 3) minimizing the number of sacrificial test wafers normally required in production; 4) minimizing development effort on new products; and 5) improving the trench depth repeatability
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The ability of IEPD to actively control etch depth is shown in Table 2. Good correlation is achieved between the targeted and the actual etch depths. There were no process changes for these wafers-only changes to the IEPD depth set-point. All depth measurements were by ex situ atomic force microscopy (AFM).
 Figure 4. Comparison of trench depths by AFM for timed and IEPD monitored wafers. |
Figure 4 shows trench depths measured by AFM across 10 wafers processed consecutively. The data for the timed etches shows a marked instability, particularly for the first few wafers processed, and results in a wafer-to-wafer uniformity of >±4% (max-min/2x mean). In contrast, the trenches monitored by IEPD have a more consistent trench depth even across the first few wafers and return a wafer-to-wafer uniformity of <±1%. The variability of the timed etches could be due to many factors including gradual conditioning of the plasma chamber, changes to the temperature of chamber furniture, or effects introduced by variability on wafer. In a sense, the root cause does not matter because the interferometer is able to compensate for these variations via the ‘floating’ etch time.
 Figure 5. Variation in endpoint times for multiple wafers and batches for: a) 1.5µm deep trenches, and b) 5.5µm deep trenches. |
Figure 5 shows endpoint times measured during the etching of multiple wafers and batches. Figure 5a is for wafers etched to a target depth of 1.5µm. The actual depths of these trenches have not been measured. However, the spread in endpoint times-the process times that correspond to a fixed trench depth of 1.5µm as given by the IEPD system-can be used to assess the variation in depths that would result if the etches were simply timed.
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Batch #1 produces a uniformity of endpoint times of ±3.2% (max-min/2x mean). When all batches from Fig. 5a are included, the uniformity is ±4.0%. These numbers are fairly typical of most timed etches. High-etch rate processes like these are more likely to suffer wafer-to-wafer variability due to hardware limitations on the system (such as the finite times taken for RF matching and the ability to switch off RF supplies at precise times).
Generally speaking, there is a trend toward shorter endpoint times as each cassette of wafers is processed, presumably due to gradual conditioning effects of the process chamber and/or temperature changes as each wafer is processed. The fact that the data for the four batches are roughly superimposed signifies that there is no memory effect of the conditioning or temperature change over the time taken to remove one batch of wafers and load another (typically 5-6 min. in this case).
Figure 5b is for wafers etched to a target depth of 5.5µm. Similar trends are seen as wafers are processed, but in this case, there is a more significant first wafer effect. The uniformity for the 11 wafers of Batch #1 is ±2.0%
Dave Thomas, Aviza Technology Inc, Newport, Wales, UK