Database inspection of 65nm logic gate CPL masks
04/01/2007
Chrome-less phase lithography (CPL) technology was introduced as a potential strong resolution enhancement technology (RET) for the application to 90 and 65nm node logic gate layers. We examined quartz (Qz) defect inspection capability on CPL masks, but only for the main chrome-less pattern and die-to-die (D/D) inspection [1]. A real CPL mask has a full tri-tone design with opaque chrome shielding as well as phase edges. Die-to-database (D/B) inspection was required to guarantee defect-free CPL masks with single-die layout. We have continuously studied and are now reporting D/B inspection capability on CPL masks that have full tri-tone design.
KLA-Tencor’s TeraScan version 10.0 software with a two-layer database inspection capability was used for the work described in this paper. Full tri-tone means there are three combinations of intensity and phase in the transmitted light: black = chrome (0%), white = quartz (100%, 0°), and gray = shifter (~100%, 180°). Thus, the inspection system has to support tri-tone images that would be constructed by a two-layer database as a reference image and also be handled at the image processing of the defect-detection algorithm.
 Figure 1. Data preparation flow of a two-layer database (that represents the mask at top) is used to create a tri-tone gray-scale image. HT = high transmission phase shift |
We have newly designed and fabricated a CPL test mask that has a production-like full-tri-tone design to check inspection applicability, and contains programmed defects to check the defect detectability and printability for Qz or Cr defects on 65nm node line patterns. Using this test mask, we report the inspection capability and defect detectability on two-layer database inspection and compare them to the defect printability analyzed by a Carl Zeiss AIMS-fab193 simulation microscope.
Functions of two-layer database inspection
Tri-tone image processing for a two-layer database inspection will now be described. Figure 1 shows the flow of the tri-tone data creation. Mask design or writing data for the first and second layers are used for the data preparation. Pattern data to which area attribute is given by data preparation is converted into a tri-tone gray-scale pixel image corresponding to the attribute in data rendering. Cr regions are assigned as 0% transmission; Qz regions are assigned as 100% transmission; and shifter regions are tentatively assigned as 50% transmission and shifter attribution.
Prior to the inspection process, a setup process is needed to specify the reference database data, inspection area, and other parameters that are necessary for database inspection. During this setup process, light calibration (LC) and pre-swath calibration (PSC) are performed for image matching between the reference (database) image and the test (mask) image. The LC of a two-layer database inspection measures and normalizes the transmission with respect to the three attribute regions: Cr, Qz, and shifter. The LC points on the mask are: the Cr region for Cr, the Qz region for Qz, and the Qz region for shifter, because the shifter can be considered to be a 100% transmission phase shift region.
PSC is processed by scanning the small area specified before the inspection to verify a match between the database image and the mask image. The PSC includes the image matching of CD bias and corner rounding, and corresponds to transmission and phase information on the shifter region. Figure 2 shows images (using a KLA-Tencor 576 P90 DH) in transmitted light on a full tri-tone CPL pattern. Figure 2a is a raw reference image and is created from data preparation; it has three tones: 0%, 50% and 100%.
After LC and PSC, Fig. 2b shows an after-processed reference image that is very well matched to the mask image in Fig. 2c. Figure 2d is a gray-scale intensity profile plot for these three images. It shows that the mask image at the shifter region is no longer constant gray; the center of the shifter region is a little brighter than that of edges. The new algorithm successfully supported the very sensitive change of brightness on the Fig. 2b processed reference. As a result, it is expected that there will be few false defect detections using the high sensitivity setting.
Experimental conditions
Design review of test mask and evaluation scheme. We fabricated a new test mask that was designed for a 65nm node (hp90) logic gate and is comprised of two patterns.
The “false check” pattern evaluates a false detection by using the production-like pattern that has a full tri-tone design; this pattern was used to adjust the sensitivity setting on the inspection system that can be inspected at a low false detection rate. Although the gray scale was in agreement between the database reference and mask images at the shifter region, the sensitivity setting adjustment is important because it is very difficult to maintain a low false detection rate at a high sensitivity setting when performing a full tri-tone database inspection. The difficulties arise because there are other error factors, e.g., the CD offset error between the Cr-covered region and the shifter region, the edge position error at the Cr-shifter edge, or pattern fidelity at the cross-point of the Cr/shifter/Qz.
A second pattern is the sensitivity check pattern that enables the evaluation of the detection capability and the printability characteristics against the designed and programmed defect on the inspection system. This pattern has two kinds of programmed defects; one is a Qz bump defect, and the other is a Cr residue defect on the shifter. The sensitivity setting specified by the false check pattern was used for the detectability evaluation because the basic design of the sensitivity check pattern is simpler than the false check pattern. The defect printability was evaluated using a Carl Zeiss AIMSfab-193 that determined whether the detectability of the inspection system was sufficient by comparing the 100% detection line of inspection and the printable line of AIMS data analysis.
Test mask design and fabrication. The basic design of the false check pattern is a production-like full tri-tone logic gate, where the design node is 65nm@1× and the minimum pitch between gates is 180nm@1×. The shifter structure is a mesa (island) type Qz shifter, so the perimeter of the shifter was etched around at 180°. The shifter width was designed at 56nm@1× and no OPC was added at any pitches. Subresolution assist features (SRAFs) are also designed and the structure of the mask places Cr on the Qz mesa. The SRAFs used on these CPL masks are composed of Cr on the Qz mesa level. Such a design reduces SRAF printability while enhancing inspectability.
 Figure 3. Cross-section diagram of four basic pattern structures. |
The sensitivity check pattern was designed at the 65nm node and constructed by using a simple line and space shifter pattern that includes four basic pattern structures: P180, P260, P390, and P390+SRAF. Each basic structure’s shifter width was optimized by considering OPC. Figure 3 shows the four kinds of basic pattern structures and the table shows the OPC design and CD measurement results by a CD-SEM.
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Designed and programmed defects are of two types: One is a 120° height Qz bump defect that contains four kinds of defect categories; the other is a Cr residue defect on the shifter that contains five kinds of defect categories. Both Qz and Cr residue defects appeared, with nominal dimensions varying from 10nm to 300nm, in steps of 10nm at a 4× mask dimension, as indicated at the top in Fig. 5.
The test mask was fabricated on a standard 6025 quartz substrate covered by AR8 opaque chrome and negative chemically amplified resist. The first electron-beam write was done at 50kV, followed by dry etching for both chrome and quartz (which was etched to a depth of 180° at the ArF wavelength). The second write step was also done using a 50kV e-beam pattern generator. But this time, positive chemically amplified resist was used, and the exposed chrome was removed by dry etching.
Evaluation tools. A number of tools and technologies were used in this experiment. D/B inspection was performed using KLA-Tencor’s 576 DUV systems (P90, algorithm: UCFdbTt45). AIMS review was done with a Carl Zeiss AIMS-fab193 (λ = 193nm, NA = 0.85, 0.85/0.57 annular illumination), and the CD-SEM system was a KLA-Tencor 8100XP-R.
Experimental results
Sensitivity setting adjustment. The final inspection parameters were defined, including the sensitivity setting, which has low false detection at the full tri-tone and a production-like false check pattern on a two-layer database inspection. The version 10.0 two-layer algorithm, called UCFdbTt45, was used for this experiment. This version supports a special plate type and specifies a shifter region’s parameters. The LC goal of the shifter was set to 240 and the phase degree of the shifter was set to 100.
LC was performed on the mask for each parameter: 1) the Cr parameter for the Cr region, 2) the Qz parameter at the Qz region, and 3) the shifter parameter at the Qz region. The sensitivity setting has five parameters: HR1, Cr-HT Edge, Line End + Corner, TriplePoint, and HR2. HR1, and HR2 are the same functionality as the previously used algorithm: UCFdbT35. Line End + Corner is the option parameter of HR1, and it is almost the same as the previous Line End and Corner of the UCFdbT35 algorithm, but it was combined into one parameter.
A function of the algorithm is that HR1 has two other options: Cr-HT Edge and TriplePoint. Cr-HT Edge defines the sensitivity at the Cr edge that is in contact with the shifter region. TriplePoint defines the sensitivity at a point where the Cr/shifter/Qz are adjacent. We did not fully examine the sensitivity optimization for these two HR1 options. TriplePoint was simply set at a low slice of 50 to avoid unnecessary false detections.
The Cr-HT Edge parameter was set as for the standard HR1 option, but it was recognized that it might be too sensitive a level. To gain the tolerance of alignment error and CD error of the second patterning process, we retained the option of reducing the sensitivity. The maximum sensitivity setting to detect Qz bump defects and Cr residue is controlled by HR1. When we used a sensitivity setting higher than 85 on HR1, an increase of false detections was observed except for shifter regions, implying that this HR1 sensitivity setting was not limited by gray level difference at the shifter regions.
Image matching confirmation. Before starting the sensitivity experiment, image matching between the processed reference and the mask image on the basic sensitivity check pattern was performed because this design contains the shifter bias for OPC. The shifter bias enables one to see the transmission difference for each shifter width.
Figure 4a shows images for the P180 basic pattern structure; it looks like a sine curve. Figure 4b shows P260 results; it has a little bit wider shifter width and the center region of the shifter is a little brighter than at the edges. Figure 4c shows P390 results; it has the widest shifter width, and the center region of the shifter is brighter, yet still looks very well-matched. Figure 4d, for the P390+SRAF structure, has a narrower shifter and a Cr-covered SRAF on the design.
 Figure 5. Defect detectability and printability of a) a Qz defect and b) Cr residue. |
All of the examples in Fig. 4 are well-matched between references and mask images. Therefore, we can expect no false defect detections, while defects that are detected will be stable during the sensitivity evaluation.
 Figure 5. Defect detectability and printability of a) a Qz defect and b) Cr residue. |
Detectability and printability of programmed defects. Figure 5a shows the detectability and printability summary of five inspection runs on Qz bump defects. Figure 5b illustrates the summary for Cr residue defects. The graph shows the results for all defect categories on all four basic design patterns indicated at the top of the column. The defect design size is indicated in the left-most column. The colored box in each cell denotes 100% detection and the listed value indicates the percentage detection out of the five inspection runs. Red horizontal lines indicate the boundary for >10% CD change as confirmed by AIMS analysis, and blue dotted lines indicate where defects would cause >5% CD change simulated at the wafer scale.
The results described above imply that all 120° Qz bumps or Cr residue defects that cause 10% CD error as defined by AIMS analysis were detected by the KLA576 two-layer database transmitted light inspection. While the detection capability of edge-type Qz defects for categories #2 and #3 is relatively easy compared to that for categories #1 or #4, it can be said that the detectability is too high on these categories and the same thing is confirmed on all categories of Cr residue defects. Further development of defect disposition methodology is expected for these defect categories.
Conclusion
We have successfully inspected a production-like 65nm node CPL logic gate pattern that has a full tri-tone design. It was confirmed that good defect detectability is possible using KLA-Tencor’s two-layer database inspection technology. The data preparation system successfully handled two-layer databases, and the rendering system created a tri-tone database image. Light calibration and pre-swath calibration produced a processed reference image that is well-matched to the mask image at the shifter region and the chrome SRAF. The TeraScan two-layer database inspection detection capability of 10% CD change on the wafer caused by defects was confirmed by AIMS analysis with a very low false defect detection rate.
Acknowledgments
The author would like to thank Cikashi Ito of KLA-Tencor/Japan and John Miller and Larry Zurbrick of KLA-Tencor for their technical support in evaluating the analysis of inspection results. The author also thanks Kouichirou Kojima, Hidemichi Imai, Hiroyuki Hashimoto, and Shiho Sasaki of DNP for their technical support of the CPL mask fabrication, inspection data analysis, and AIMS data analysis.
CPL is a trademark of ASML MaskTools. AIMS is a trademark of Carl Zeiss. AR8 is a product name of HOYA.
Reference
- Yasutaka Morikawa, “An In-process Strategy for Defect-free CPL Reticles,” Solid State Technology, p. 42, December 2005.
Yasutaka Morikawa received his BS in chemical engineering from Tokushima U. and is a senior expert in the Electronic Device Lab at Dai Nippon Printing Co. Ltd., 2-2-1 Fukuoka, Fujimino, Saitama 356-8507, Japan; ph 81/492-78-1687, e-mail [email protected].