Intel unveils 45nm chip with high-k, metal gates
03/01/2007
Claiming “a significant breakthrough in transistor technology,” Intel Corp. says it has advanced its 45nm process technology from a SRAM test chip unveiled in Jan. 2006 into working 45nm microprocessors, chips that incorporate a hafnium-based high-k dielectric material and a new combination of metals for the transistor gate electrode. The new “Penryn” transistor will start shipping in volume by year’s end on various systems, including those with Microsoft Vista OS.
“These are not lab devices, not just research results,” said Mark Bohr, Intel senior fellow, in a conference call presenting the details of the 45nm process. “We have both nMOS and pMOS, providing better performance and lower leakage,” and the chips are “manufacturable in high volume,” he said, adding that the performance specs are “better than our competitors, including those using SOI.”
The Penryn 45nm processor, which utilizes the same features, interconnects, high-k features, and design rules as the 45nm SRAM test chip (0.346µm2 cell, 153Mbit density, 119mm2 chip size), promises 2× increased transistor density, ~30% reduction in transistor switching power, 5× reduction in source-drain leakage, and >10× reduction in gate oxide leakage. The reduction in gate leakage results from the fact that the gate oxide thickness can be increased using the hafnium-based high-k dielectric, which is produced by atomic layer deposition (ALD)-though Intel did not indicate the type of ALD used (ternary or quadrinary alloying elements, or amorphous vs. crystalline phase) or any integration challenges. The company also did not disclose specifics of its new combination of metal materials for the transistor gate electrodes, requiring one for nMOS and another for pMOS. The new transistors still maintain strain in the channel regions for maximum carrier mobility.
 Figure 1. How Intel’s 45nm HK+MG transistor stacks up. (Source: Intel Corp.) |
Bohr showed a TEM micrograph (see Fig. 1) that suggested a 2.5-3.0nm total dielectric thickness (which must include at least one monolayer each for upper and lower barriers) for the gate insulator, instead of the 1.2nm (~six atomic layers) silicon oxide layer grown in Intel’s 65nm chips.
The shift to 45nm processes isn’t as daunting from a manufacturing standpoint as perhaps feared. Bohr explained that the 45nm high-k, metal gate (HK+MG) process utilizes “cost-effective” 193nm dry lithography techniques and most of Intel’s production equipment. The few added process steps amount to only “a small single-digit percentage increase” in manufacturing costs, “a small price to pay when doubling transistor density,” he said.
 Figure 2. Intel’s 45nm yield-learning curve tracks the last three nodes. (Source: Intel Corp.) |
All these changes result in new process integration challenges and new yield loss mechanisms, so it might be expected that it would to take a while longer to ramp yield. Amazingly, Intel also showed a 45nm yield-learning curve that tracks the last three nodes (see Fig. 2).
At a press show-and-tell at Intel HQ, the company demonstrated the 45nm Penryn chips running five computers, including 80W chips for servers, 65W chips for desktop computers, and 35W chips for notebooks, all shipped down the night before from testing in Intel’s validation lab in Folsom, CA. Later versions of the 45nm-generation devices will have even lower power consumption (down to 5W), while others would run significantly faster than 2GHz. Steve Smith, VP of Intel’s DEG Group Operations, indicated that the very first 45nm wafers to come out of the fab assembled and packaged were able to boot an OS “within two or three hours.”
The dual-core version of Penryn has about 410 million transistors, and twice that for quad-core. Most of the 45nm transistor budget increase is in increased cache, with additional computing capabilities including 50 new streaming SIM extensions and SSE4 instructions (a mix of integer and floating-point instructions).
The first 45nm devices will come out of Intel’s D1D fab in Oregon in 2H07, followed “a few weeks” later by Fab 32 in Arizona. Intel’s Fab 28, under-construction in Israel, will be ramping the 45nm process by 1H08. -E.K., M.D.L., J.J.M..
NEC leads with cost-effective 3D and ULK interconnects
There are many ways to interconnect two transistors, and as the industry the looks at maximizing density and speed with continued dimension shrinks, the challenges increase. In particular, it becomes more challenging to keep manufacturing costs low while trying to control processes needed to form ever more complex structures. NEC has been involved with the development of very high-performance chip interconnects-both 3D stacking of chips in a single package, as well as porous ultralow-k on-chip dielectrics-at what appears to be relatively low cost.
NEC Electronics, Elpida Memory, and Oki Electric Industry, supported by the New Energy and Industrial Technology Development Organization (NEDO), have combined resources in Kanagawa, Japan, to demonstrate a new 3D high-performance DRAM package using bumps, through-silicon vias (TSVs), a “feedthrough interposer” (FTI), and a redistribution layer. Simulations already show 3Gbps data transfer capability, and “within a half-year we should get better results,” said Masao Fukuma, SVP, NEC Electronics Corp., in an exclusive interview with SST.
Elpida does the DRAM fabrication after embedding the TSVs. Since the vias must withstand high-temperature transistor formation processes, metals are ruled out and doped poly-Si is used as the conductor. Instead of a single via for each conductor, this work uses regular arrays-4×4 vias for signal and 6×6 or 8×8 vias for power-surrounded by a trench ring to reduce parasitic capacitances (Fig. 1). Each via is 2µm in dia., so that 25:1 aspect ratios can be uniformly filled with ~1µm poly-Si in a relatively short deposition step. A hardmask 1.5µm thick was sufficient for ~50µm deep etching. After via etch, isolation, and poly-Si deposition, topside CMP provides the smooth top surface for subsequent DRAM processing.
Vias are exposed by temporarily bonding the processed wafer to a glass “handle” wafer for back-grinding and CMP to a thickness of 50µm. After the poly-Si TSV arrays on the backside are exposed, Cu/Ti/Al UBM deposition occurs after careful cleaning to ensure ohmic contact. Then over 1000 TSVs are connected with 50µm spaced microbumps. This wafer thinning and bumping sequence can be repeated to stack up multiple wafers.
The DRAM chips are stacked on top of a FTI that is 33mm2, with 520 pins at 1mm BGA pitch (Fig. 2). The final package looks like a standard BGA type, but contains eight layers of DRAM. From first principles, these poly-Si TSVs seem to be very manufacturable, and it is likely that they will be used to stack logic and other nanometer-era chips too.
Seamless ULK for 32nm
On-chip nanoscale dielectric structures must be complex to balance the inherent trade-off between dielectric constant, mechanical strength, and cost of manufacturing. In particular, barrier layers to provide final mechanical strength or a convenient etch-stop during processing often increase the dielectric constant excessively. NEC, working with the support of Japanese government program MIRAE, has developed what is claimed to be the world’s first 32nm node multilayer interconnect technology, and it has layers without seams.
With 100nm pitch and 50nm diameter vias, the layers do not have discrete transitions due to gradual compositional changes achieved in a one-chamber CVD process. This work builds upon the “seamless low-k SiOCH stack” (SEALS) dielectric presented in mid-2006 at the VLSI Symposium.
The molecular pore stacking (MPS) line-level ULK dielectric (k = 2.45) is formed using a six-member siloxane ring precursor, while a 24.8GPa modulus SiOCH with k = 3.1 is formed for the hardmask using just a chain-monomer precursor. The plasma co-polymerization of both precursors, provided by Tosoh Corp., creates a SiOCH film with slight porosity, 12.6GPa modulus, and k = 2.8 for the via level.
Each layer of the stack is thus tuned for differing adhesion, porosity, and modulus values, and a SiCN layer is used for a cap. The pores in the MPS layer average 0.35nm in dia.
“The biggest problem with low-k dielectrics is water intrusion,” said Dr. Yasunori Mochizuki, chief manager, research, system devices research laboratories, NEC Corp. in an interview with SST. “When we make the pore size smaller than 1nm, then we have negligible water entering the low-k.”
The lack of discrete interfaces reduces the overall defects within the stack by three orders of magnitude, result-ing in 83 fF/mm interline capacitance for 50nm spaces. The resulting “density-modulated low-k film stack” has sufficient compositional differences between the layers to allow for dual-damascene etching without the need for additional etch-stop layers. Optical emission spectroscopy (OES) of the plasma during etch provides a sufficiently clear signal in time for end-point control. -E.K.
Controlling line-edge roughness in EUV resist with sturdy, small molecules
Tokyo Ohka and Hitachi have demonstrated patterns with 28nm half-pitch resolution, with EUV resist made using small molecules that eliminate much line-edge roughness.
The relatively size of the individual polymer molecules in conventional resist creates a problematic uneven edge in very small features at 32nm and beyond, though these polymers also provide the high mechanical strength that allows the resist to withstand etching and developing.
In work supported by the New Energy and Industrial Technology Development Organization (NEDO) and the Association of Super-Advanced Electronics Technologies (ASET), the companies designed a molecule with molecular weight an order of magnitude less than those used in current resists, but that still maintained etch resistance and developing characteristics similar to existing polymer-based products, reports SST partner Nikkei Microdevices.
The resist uses a new small-molecule polyphenol with molecular weight of around 1000, while the typical polymer weight is around 10,000. With resist sensitivity of 12.2mJ/cm2, the LER of printed 45nm features was 3.6nm, matching that of the best polymer resists (see figure). Features at 28nm half-pitch were also comparable to those made with leading-edge conventional resists. These initial results were at exposures on the edge of the capability of the EUV lithography tool used, suggesting the approach may have considerable potential to be extended to smaller geometries.
Tokyo Ohka plans to start supplying samples of the resist for EUV and e-beam exposure this spring, targeting commercial sales in 2010. -P.D.
IBM, SEMATECH: We’re using high-k, too
Hours after Intel announced its 45nm transistors that use high-k dielectric and metal gates for shipment later this year, SEMATECH and the IBM Common Platform Alliance both released statements indicating that they, too, are in the final stages of tinkering with the technologies, and will be discussing details at upcoming industry venues.
IBM says that its work with partners AMD, Sony, and Toshiba has led to insertion of high-k metal gates into a manufacturing line at its East Fishkill, NY facilities, and will be incorporated into 45nm chips starting sometime in 2008. Like Intel, IBM indicated that adding the high-k process to its manufacturing lines did not require major tooling or process changes.
Mukesh Khare, senior manager of IBM Research, gave a few extra details about their process, telling SST only that they are using “conventional processing” and are not “cutting any corners,” and that further details will be presented sometime around midyear. Although high-k could be used “anywhere we like,” the first application would be for high-performance devices, with an eye toward IBM’s internal Power work, he said. Volume production ramp is scheduled for sometime in 2008, but Khare noted that work is focused in Fishkill, and so IBM will be first to ramp production-then it’s up to specific partners to decide when and how to take the technology back to their own facilities for production.
Meanwhile, SEMATECH says it has successfully integrated pMOS and nMOS metal gates into highly scaled CMOS devices with low threshold voltage “similar to conventional polysilicon/SiO2 devices,” and with ultrathin equivalent oxide thicknesses “in the range of 1.0-1.2nm.” The group says the CMOS devices were fabricated with conventional gate-first, high-temperature processing flows, without using substrate counter-doping or other extraordinary or complicated measures, and showed no reduction to drive currents or other performance metrics.
Earlier this year, NEC Electronics revealed a CB-55L cell-based IC using its 55nm “UX7LS” process technology, which the company claims uses high-k dielectric to reduce leakage current, and DFM techniques including on-line/on-the-grid layout to prevent excessive parameter variations. The technology initially will be available only to makers of digital cameras and other portable devices. -J.J.M.