Stretching silicon mobility with strain engineering
03/01/2007
For years, semiconductor manufacturers depended on a happy coincidence: smaller transistors are less expensive to manufacture and also deliver better performance. They cost less to produce because most manufacturing steps process the entire wafer area at once. With the important exception of lithography, the cost per wafer is the same whether the wafer contains ten devices or a thousand. Thus, fitting more devices in the same space decreases the cost of each device. This observation is the essence of Moore’s Law.
The second half of the happy coincidence is the reduction in switching time for smaller transistors. Put very roughly, the shorter the gate length (Lg), the less distance carriers have to travel, and the more quickly the device can switch between the on and off states.
This lucky combination of improved performance at reduced cost has held for most of the semiconductor industry’s history. Consumers got more performance for less money, manufacturers made consumers happy while cutting their own costs, and the Information Age dawned.
Then a serious obstacle appeared, in the form of gate oxide scaling limits. As the gate length of a transistor scales down, all the other transistor dimensions must scale as well.
In particular, a shorter gate requires a thinner gate dielectric. The gate dielectric creates a capacitor between the gate and the channel. Applying a voltage to the gate changes the distribution of charges in the channel, allowing current to flow. Shorter channels have higher current density, and therefore require more gate capacitance to switch the transistor. The capacitance (Cox) depends on the thickness (Tox) and permittivity (εox) of the gate dielectric so that Cox ≈ εox/Tox.
The permittivity in turn depends on the dielectric constant (k). If the dielectric constant of the gate dielectric remains the same, the dielectric layer must become thinner. Unfortunately, thin gate dielectrics allow more leakage current, increasing the power consumption of the circuit and blurring the transition between the on and off transistor states. When the gate oxide thickness falls below about 1.2nm, the leakage becomes so significant that the circuit is no longer practical. (See Ref. 1 for a more complete discussion of scaling issues.)
Manufacturers can change the tradeoff between capacitance and leakage by using a different gate dielectric: a higher dielectric constant gives the desired capacitance with a physically thicker, less leakage-prone layer. (Part 3 of this series will discuss gate dielectric materials in more detail.) Manufacturers can also improve performance without scaling Lg by using a different channel material: the improved mobility offered by semiconductors other than silicon allows faster switching at any give gate length. (See Part 1 of this series: “Turning to an old friend, device engineers are reconsidering germanium,” in SST’s February 2007 issue.) Finally, manufacturers can improve performance by boosting the mobility of the silicon-based transistors they already have.
It turns out that mobility enhancement works remarkably well. Lattice strain has been used to enhance mobility in production devices since the 90nm technology node, and models presented at the 2006 IEEE Electron Device Meeting (IEDM) suggest that a strained silicon lattice can give hole mobilities up to 4× the unstrained value, and electron mobilities up to 1.8× the unstrained value [2]. With gate length scaling stalled and new materials still unproven, mobility engineering has become the single most important contributor to IC performance improvement.
There are actually several different ways to manipulate carrier mobility in the silicon channel. Each affects circuit performance in a different way, because each has a different impact on the underlying silicon band structure.
Uniaxial strain
The most commonly used approach, known as uniaxial or process strain, is at least superficially the most complex. Designers modify the transistor structure to apply tension (for nFETs) or compression (for pFETs) to the channel. For example, because the SiGe lattice is larger than the silicon lattice, replacing the silicon source and drain regions with SiGe compresses the channel, improving hole mobility. Increasing the germanium concentration gives a larger lattice, more strain, and higher hole mobility. Strain cannot increase indefinitely, however. The lattice, like any system, tries to find the configuration with the lowest energy. For instance, the lowest energy might be achieved by forming dislocations at the Si/SiGe interface. Not only are such defects undesirable in themselves, but dislocations also relax the lattice strain, and therefore reduce the mobility enhancement.
According to work presented at the 2006 IEDM by researchers at Infineon, significant strain relaxation occurs as the germanium concentration increases. The Infineon group was able to achieve a higher peak germanium concentration without relaxation by using a graded deposition profile: germanium concentration was highest near the channel, but lower near the wafer surface [3].
While SiGe source and drain regions increase hole mobility by compressing the channel, electron mobility enhancement requires tensile strain, usually applied by means of a SiN cap layer, or stress liner. With different SiN deposition conditions, stress liners can also provide additional compressive strain for hole mobility enhancement.
 Figure 1. Change in horizontal component of stress with liner thickness and device pitch. (Courtesy: Toshiba Corp. [4]) |
The space between adjacent transistors serves as a foundation, anchoring the stress liners. As the transistor pitch shrinks, so does this space. At the 2005 IEDM, researchers at Toshiba showed that decreasing transistor pitch moves the point of maximum stress upward, away from the channel [4] (Fig. 1). Though stress liners appear to scale successfully to at least the 45nm technology node, their prospects beyond that are unclear.
A closely related uniaxial strain technique, stress memorization, first amorphizes the polysilicon gate, then anneals it while constrained by a tensile cap layer. The stored stress remains even after removal of the cap layer. Thus designers do not have to worry about the electrical impact of an additional layer, but can simply apply stress to their existing devices. Stress memory structures impose additional thermal budget constraints, as excess heating can allow the stored strain to relax. Stress memory techniques are applicable to any material, but the impending replacement of polysilicon with new gate materials will force manufacturers to revise their implementations. For reasons that are not yet clear, stress memorization techniques appear to degrade pMOS characteristics, while improving nMOS performance.
Embedded SiGe, stress liners, and stress memory techniques appear to be additive: a device can successfully apply all three and achieve the sum of their mobility enhancements. Though uniaxial strain requires changes to the fundamental transistor process, it is popular because it appears to achieve more performance improvement with less stress than biaxial strain techniques do.
Biaxial strain
Biaxial, or global strain, in contrast, has the important advantage of pitch independence. While uniaxial strain fields applied to individual devices will change with feature size, biaxial strain fields applied at the wafer level do not. This approach is somewhat easier to model, as the strain level remains the same for devices with different dimensions and is unchanged by design shrinks.
Consistent biaxial stress is achieved by depositing the silicon device layer on top of a SiGe underlayer. The mismatch between the two lattices creates strain. For bulk silicon devices, manufacturers grow a graded SiGe layer (typically 2-3µm thick) on top of a standard silicon wafer, gradually increasing the germanium concentration to the desired value. Ideally, the SiGe layer should be fully relaxed, with little or no residual strain. A relaxed layer is more stable during thermal cycling, and likely to behave more consistently throughout the wafer process. In practice, the need for a relaxed SiGe underlayer means that each sublayer must be relatively thick. Lattice mismatch at the interface between sublayers causes dislocations and other defects. As the layer thickness increases, these defects “grow out,” and a uniform, relaxed lattice forms.
For the same reason, the silicon device layer deposited on top of the SiGe strain layer must be very thin, typically between 20−30nm. Thick layers will nucleate dislocations in order to accommodate the lattice mismatch strain. With a thin silicon device layer resting on top of a thick Ge-rich underlayer, there is little buffer against germanium diffusion. Moreover, the germanium growth process is time-consuming and adds significantly to the total wafer cost.
So far, these considerations have limited interest in bulk strained silicon. Biaxial stress of silicon-on-insulator (SOI) wafers appears to be somewhat more promising. Most SOI wafers are made by a layer transfer technique. After bonding a thick oxide grown on a silicon handle wafer to a substrate wafer, most of the handle wafer is removed. The transfer process inverts the original material stack: the high quality thermal oxide on the handle wafer becomes the buried oxide in the finished SOI wafer. Scientists at Soitec, originators of the so-called Smart Cut process, have shown that it is widely applicable for the transfer of complex stacks to both silicon and other substrates.
To build a strained silicon-on-insulator (sSOI) structure, Soitec starts with a silicon-on-SiGe handle wafer, similar to the bulk strained silicon/SiGe stack described above. After oxidation, the process transfers just the oxide and silicon layers to the substrate wafer. The graded SiGe structure remains on the handle wafer, ensuring that neither its defects nor its potential for germanium contamination will follow the strained silicon layer into the fab.
Though biaxial strain does not achieve the same mobility enhancement that uniaxial strain can, it is additive with uniaxial strain. It gives companies, especially those already committed to an SOI-based roadmap, another lever they can use to adjust mobility. According to Suresh Venkatesan, senior director of CMOS platform device development at Freescale Semiconductor, externally applied strain is less useful as the pitch drops, making sSOI structures more appealing. Freescale has been using SOI for five device generations, Venkatesan says, and plans to continue to do so. He expects sSOI will be key to the company’s approach.
How strain helps
Uniaxial and biaxial strain techniques both manipulate the energy band structure of silicon. To understand why they achieve different effects, it’s helpful to examine the physics of strain a bit more closely.
Textbooks often show energy bands as simple linear structures. At this level of abstraction, carriers move easily with the applied potential until they encounter the region near a junction. Yet the actual band structure is a complex hybrid of the energy levels surrounding all of the atoms in the silicon lattice. As a carrier drifts through the material, it encounters the potential fields surrounding each atom in the lattice. A more accurate model of silicon’s band structure reveals that it is actually a 12-fold symmetric surface in three-dimensional space [2]. As a result, the effective mass, and therefore the carrier mobility, fluctuates as the carrier moves in the <100> plane used for most integrated circuits.
Applying stress forces charges in the lattice to take new positions, thereby changing the band structure. Both biaxial and uniaxial stress break the 12-fold symmetry of unstrained silicon. Under biaxial stress, the effective mass is approximately constant in the <100> plane, indicating a reduction in scattering. However, the effective mass remains near the nominal (unstrained) value. The mobility improvement observed in biaxially strained silicon thus appears to be due to reduced scattering alone. This reduction in scattering has a significant mobility impact only for high stress values, in excess of 1GPa.
Uniaxial stress, in contrast, reduces both scattering and in-plane effective mass. Carriers in uniaxial strained silicon have ~40% lighter effective mass than that seen in unstrained or biaxially strained silicon [5]. This model agrees with experimental results that shows uniaxial stress delivers more mobility enhancement at lower stress levels than biaxial stress.
Hybrid wafers
The relationship between band structure and mobility points the way to another method for mobility engineering. The band structure shown in Fig. 2 is three-dimensional, but current flow in a transistor is essentially two-dimensional, in the plane of the substrate. Below the 32nm technology node, in fact, the channel takes on many characteristics of a one-dimensional nanowire. Device designers can choose what portion of the 3D band structure to use, by defining the orientation of the channel relative to the substrate, and by choosing a different substrate orientation. While CMOS devices have historically used <100> oriented substrates, <110> and <111> orientations are also possible. Changing the orientation of the channel causes current to flow along a different slice of the energy band structure.
NFET devices achieve their best performance when devices are oriented along the <100> direction, while pFET devices benefit from a <110> alignment. Yet both nFETs and pFETs must coexist in each integrated circuit.
As explained above, layer transfer techniques can be used to place nearly any device layer on nearly any substrate, so placing a <110> top layer on a <100> substrate is straightforward. Starting from this structure, researchers at IBM created a hybrid orientation wafer by using an amorphizing implant to disrupt the structure of the nFET device regions. An annealing step promoted solid phase epitaxial (SPE) regrowth, using the underlying <100> substrate as a template [6] (see Fig. 3).
If shallow trench isolation (STI) takes place before SPE, then the only growth template available is the <100> substrate, and correct orientation is assured. However, the IBM group found that defects formed at the interface between the regrown silicon and edges of the STI trench. An alternative approach performs SPE first, before STI. Here, growth takes place vertically, from the <100> substrate, and laterally, from the adjoining <110> pFET regions. Defects occur at the intersection of the two growth fronts. However, the subsequent trench etch step removes the defective regions, leaving a defect-free, hybrid orientation device surface.
Thompson showed that aligning the pFET channel with the <110> direction can increase mobility 2−3× [2]. However, the mobility enhancement due to orientation may not be additive with either biaxial or uniaxial strain techniques. Strain enhances mobility because it breaks the 12-fold symmetry of the silicon band structure. When manufacturers manipulate device orientation, they are already exploiting a low symmetry, low effective mass region of the band structure. It is not yet clear how much additional benefit strain engineering can provide.
From simple uniaxial stress liners to complex hybrid orientation wafers, process engineers can choose from a whole library of strain engineering techniques. Yet each of these, as Freescale’s Venkatesan points out, adds additional process steps and additional costs. High performance devices may use several different approaches, combining stress effects to wring as much performance as possible out of the circuit. For high performance devices, uniaxial strain is the obvious choice. Low power devices, in contrast, are often aimed at high volume, low cost consumer applications. In this sector, simpler approaches may be more cost effective, even if they give objectively smaller mobility enhancements.
References
- Scott E. Thompson, et al., “In Search of ‘Forever,’ Continued Transistor Scaling One New Material at a Time,” IEEE Trans. Semi. Mfg., Vol. 18, p. 26, 2005.
- S.E. Thompson, et al., “Future of Strained Si/Semiconductors in Nanoscale MOSFETs,” IEDM Tech. Digest, 2006.
- J-P. Han, et al., “Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices,” IEDM Tech. Digest, 2006.
- A. Oishi, et. al., “High-performance CMOSFET Technology for 45nm Generation and Scalability of Stress-induced Mobility Enhancement Technique,” IEDM Tech. Digest, 2005.
- S.E. Thompson, et al., “Key Differences for Process-induced Uniaxial vs. Substrate-induced Biaxial Stressed Si and Ge Channel MOSFETs,” IEDM Tech. Digest, 2004.
- Haizhou Yin, et al., “Direct Silicon-bonded (DSB) Substrate Solid Phase Epitaxy (SPE) Integration Scheme Study for High-performance Bulk CMOS,” IEDM Tech. Digest, 2006.
Katherine Derbyshire is a contributing editor at Solid State Technology. She is the founder of consulting firm Thin Film Manufacturing, e-mail [email protected].