A sub-100nm manufacturing technique for for hot-spot removal
03/01/2007
In today’s advanced integrated circuits (ICs), critical manufacturing challenges such as hot spots are becoming routine phenomena. These hot spots will occasionally occur at the fab’s nominal lithography process conditions, yet under process corner conditions, they become a severe problem. Once hot spots are identified, fabs today lack a well-established mechanism for their removal. Current inefficient options include: a) waive the process-corner risks by sacrificing yield, b) reject the tapeout for additional layout modifications and thus introduce extensive delays, or c) re-run optical proximity correction (OPC) with a revised recipe in hopes that it will not create new hot spots or shift the process window in an unfavorable direction for the entire design. To efficiently remove hot spots, we first inspect the OPC data to identify a typical volume of real and potential hot spots.
Sub-100nm database
We conducted the experiment on a sub-100nm DRAM design from ProMOS Technologies to validate the effectiveness and the production worthiness of this hot-spot removal approach. The OPC layer of the chip was created using a production recipe that includes rigorous lithography simulation and model-based OPC decorations. The process used was a metal zero layer with 110nm half-pitch, attenuated phase shift mask, and annular illumination. Model calibration data from wafers in the fab were used to determine the nominal process conditions (F0E0). For process corner simulations, we established a process window at 15% in exposure latitude (EL) and ±100nm in depth-of-focus (DOF). After analyzing the database for lithography interactions and process effects, we selected a critical area of the chip layout where line-edge, line-end, and space-end lithography interactions dominate.
Process corner LRC
To inspect the design for hot spots, Aprio’s Halo-Sim was chosen to simulate the database through process corners in order to emulate the fab’s process variations [1]. Initial inspection on the DRAM database was performed at nominal focus and exposure (FE) conditions, or at the fab’s optimal process conditions. No hot spot was found in the database as expected, since the original OPC decorations were created with a production OPC recipe that calls for vigorous lithography simulation in conjunction with aggressive model-based OPC. Next, inspection of the DRAM database was performed across a matrix of nine FE conditions. The process corner matrix covered E0 ±15% and F0 ±100nm. A total of 164 device-impacting hot spots were found. These 164 hot spots were grouped into categories based on defect rules that were used to guide fixing priorities. Among these categories, “necking” and “bridging” hot spots were chosen for the hot-spot removal procedure, as they have the most severe impact on device performance and yield.
Reconfigurable OPC
Hot spots in the FE window indicate weak patterns that need additional corrections to the OPCs, obviously falling outside the original master OPC recipe. Thus, a new OPC recipe needs to be developed. However, hot spots are localized problems that should not be corrected with a global change to the entire chip. Each hot-spot category is unique in its own lithography behavior and requires localized computation to achieve optimal correction. For example, the localized lithography computation for one hot-spot category can be different than, or opposite of, the one used for another category, and it may negatively impact the rest of the chip if applied globally. Thus, re-running conventional full-chip OPC with a revised recipe usually leads to new hot spots.
 figure 1. The reconfigurable OPC process with Halo-Fix runs a local OPC on identified problem areas. |
Aprio’s technology allows OPC repair to be performed on a specified portion of an OPC-corrected layout [2]. This technique can localize the computation of the lithography effects while simulating complex polygon interactions within the ring or “halo” of the target areas in order to obtain accurate convergence of the repaired data into the original OPC layout. Other areas that do not require reconfiguration or fixing will be left untouched. Figure 1 graphically illustrates the reconfigurable OPC flow.
Since this technique performs reconfiguration on a set of very small areas of the design rather than on the full chip, the run time is substantially shorter than conventional OPC methods. Furthermore, the approach allows for localized fixing strategies to be applied to each hot-spot category, resulting in the most accurate correction. Finally, since the technique does not generate new hot spots, it ensures manufacturing convergence and increases the common process window for the entire design.
Model- and rule-based fixing
Both model-based and rule-based OPC were utilized in the fixing procedure. Model-based fixing allows for a more favorable model to be applied in the hot-spot areas of the design. Rule-based fixing offers a faster turn-around time compared to model-based fixing, and can be used for fixing relatively isolated hot spots. In this experiment, model-based fixing was utilized for the removal of “bridging” hot spots; and rule-based fixing was utilized for the removal of “necking” hot spots.
The previous process corner LRC results indicate that the “bridging” hot spots occurred at the low dose side of the process map. Thus, to remove these hot spots, a new process corner model was generated by shifting the FE conditions by -15% in exposure latitude and ±100nm in DOF. This is a localized process corner shift that will not negatively impact the remaining parts of the design that already passed LRC. Figure 2 shows the “bridging” error locations at defocus, the localized OPC fix at defocus, and the fixed OPC at nominal. These resist image contours confirm that the hot spot at defocus was successfully removed and that the fix created a more robust solution even in the original F0E0.
Next, rule-based fixing was applied for the removal of “necking” hot spots. To fix these hot spots, additional OPC bias was used in a rule-based OPC fix run to minimize the edge placement error (EPE) between the drawn layout and the manufactured silicon. Figure 2 shows the “necking” locations at defocus, the localized OPC fix at defocus, and the fixed OPC at nominal. The improvement after the rule-based OPC fix is clearly shown.
Finally, to verify that the identified hot spots had been successfully removed, full-chip process corner LRC was run again to ensure that lithography interactions and process variations were accurately accounted for during the fixing procedure. No hot spot was found with the same nine FE conditions. This step confirms the substantial enlargement of the process windows. This approach improves turnaround time by eliminating the need to re-run OPC on the entire layout.
Conclusion
Reconfigurable OPC fixing was utilized on an advanced DRAM chip to localize the computation of the lithography effects at the hot-spot areas and to accurately converge the fixed OPC results into the original O PC decorated database. As a result, the process window was enlarged significantly from less than <15% EL and ±100nm DOF.
Acknowledgments
Halo is a trademark of Aprio Technologies.
References
- B. Su, et al., “Litho. Process Window Enhancement Using Integrated Design Defect Detection and Fix,” Proc. SPIE, pp. 1-9, 6283, 2006.
- R.D. Morse, et al., “Using Reconfigurable OPC to Improve Quality and Throughput of Sub-100nm IC Manufacturing,” Proc. SPIE, pp. 1-8, 6154, 2006.
Contact Melissa Anderson at Aprio Technologies, 2520 Mission College Blvd., Suite 201, Santa Clara, CA 95054; ph 408/855-8088, x217; e-mail [email protected].