Freescale’s process and fab strategy puts a new spin on MRAM
03/01/2007
Freescale was recently honored with a product award for its magnetoresistive random access memory (MRAM) product, the Freescale MR2A16ATS35C 4-Mbit MRAM. It is fabbed in a 0.18µm six-metal process, with a 256K×16-bit configuration, runs on a 3.3V supply, and is available in a 44-pin TSOP type-II package. Such an unusual part always catches our attention, so we couldn’t resist looking inside to see how Freescale put it together.
The core operating structure of an MRAM device is a magnetic tunnel junction (MTJ). The bit state is stored as the relative magnetization orientation of two magnetic layers in direct contact with a tunnel barrier, with an anti-parallel orientation (high state) having a higher junction resistance than a parallel orientation (low state). The bit state is read out by passing a current through the junction and comparing the junction voltage to a known reference [1].
 Figure 1. Freescale MRAM magnetic tunnel junctions, top view. (Source Chipworks) |
The Freescale MRAM cell has these multilayer magnetic tunnel junctions placed diagonally between two high-current write line conductors formed in metal 4 and metal 5 and arranged at right angles to each other. In Fig. 1, the chip has been de-layered to expose an array of MTJ structures, showing the smaller top plates overlaying the larger bottom plates. The lower write lines can just be seen under the array of junction plates. The contacts seen in the center of the upper plate go to a common top electrode, and those at the top edge of each lower plate go down to an isolation (select) transistor in the substrate.
 Figure 2. Schematic of magnetic tunnel junction structure. |
The schematic in Fig. 2 illustrates the principle of operation. The device employs magnetoresistive tunneling across an insulating tunnel barrier, sandwiched between two synthetic antiferromagnetic (SAF) layers. The top SAF layer is “free” (i.e., its magnetic moment can be programmed), and the bottom SAF is a “fixed” (not programmable) reference layer.
 Figure 3. SEM cross-section of MTJ structure. (Source Chipworks) |
In Fig. 3, we can see the lower M4 write lines in cross-section, and a linear section of an upper M5 write line, with the magnetic tunnel junction structure in between. (There are some voids from sample preparation in this image.)
 Figure 4. TEM image of the MTJ structure. (Source Chipworks) |
Both the top and bottom SAF layers are actually three sublayers: two ferromagnetic layers separated by a nonmagnetic spacer. The free ferromagnetic sublayers use a magnetically programmable material with almost balanced magnetic moments. This allows the magnetic moments to rotate like a pair of linked “clock hands” when the magnetic field is applied. The tunnel barrier is aluminum oxide. The TEM image in Fig. 4 shows the multiple layer structure.
 Figure 5. MRAM toggle switching sequence. (Source: Freescale) |
The use of this type of structure, in its diagonal orientation, allows the magnetic moments to be toggled 180° using the same two-phase pulse sequence regardless of state and using both write lines. This requires a pre-read to see if a write sequence is needed, but protects the datum state from a single pulse on either one of the write lines (see sequence in Fig. 5).
The write lines themselves have some interesting structural quirks to optimize the magnetic coupling to the MTJ. Not the least interesting is that they are made of copper, whereas the bond pads and lower metal layers are the conventional aluminum consistent with the 0.18µm process. Presumably, this is to allow higher current density, to give a higher magnetic field, and to keep the cell pitch down. The inlaid damascene structure also aids the use of magnetically permeable cladding layers, which concentrate the magnetic fields. Freescale claimed double the magnetic flux when these layers were added [2].
 Figure 6. TEM images of the M4 write-line structure. (Source Chipworks) |
The cladding in the bottom write line focuses the magnetic field upward into the tunnel junction. This is elegantly achieved by adding a NiFe layer to the barrier layer structure of the damascene line, seen schematically in Fig. 2 and in a TEM cross-section in Fig. 6. The NiFe is laid down as an outer barrier layer and then the usual Ta-based barrier before filling the trench with copper.
The upper write line is more difficult to make; to focus the field down on to the MTJ, the cladding needs to be on the top and sides of the line (see Fig. 2).
 Figure 7. TEM images of the M5 write-line structure. (Source Chipworks) |
Figure 7 illustrates how Freescale achieved this by laying down a Ta barrier layer, followed by the NiFe layer on the bottom and sidewalls of the trench. Next, the NiFe is sputtered away from the trench bottom and another Ta barrier layer is deposited.
The trench is filled with copper and planarized as usual, and nitride and oxide metal cap layers are deposited. These are masked and etched to expose the top of the M5 copper in the memory array. A second set of NiFe and Ta layers are deposited and then polished back to remove the excess and isolate the lines, leaving “wings” at each line edge. It is a relatively complex process, but it achieves the desired end.
That covers the basics of the MTJ. With the lower metal levels being aluminum and M4 and M5 copper, the device is one of the few parts that we have seen with a true hybrid metallization structure, as distinct from the copper metal with Al bond pads that we see in most 130nm and smaller parts.
This actually is a clue to the fab history of the part. When the frontend structure (i.e., transistors +M1-M3) was studied, it looked very similar to TSMC’s 0.18µm2 process that has been seen in quite a few other devices. Discreet inquiry revealed that the frontend was indeed fabbed out to TSMC, and then the wafers were shipped back to Chandler to add the MRAM structure.
Given that the Freescale marketing personnel have been saying that a major advantage of this MRAM technology is that it is a backend addition to conventional CMOS, and therefore very suitable for embedded use, this fab sequence would seem to be a clear demonstration of that statement.
As a manufacturing strategy, it also makes a lot of sense since it keeps the wafer cost down to foundry levels and also allows tighter inventory control for a speculative product launch. A stock of frontend wafers can be kept, while the backend can be added as needed by order volume.
The MRAM cell size of 1.3µm2 compares well with SRAM cell sizes of that generation. One of the target markets is battery-backed SRAM storage used for applications such as data logging, and the device is packaged with an SRAM-compatible pinout. With this part, Freescale has come up with a fascinating technology. It could have some disadvantages in terms of price/performance, but as a solution that requires zero power to store data, it will find some interesting applications in automotive, aerospace, and similar markets.
References
- P.K. Naji et al., “A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM,” IEEE ISSC Dig. Tech. Papers, Vol. 44, Feb 2001.
- M. Durlam et al., “A Low-power 1Mbit MRAM Based on 1T1MTJ Bit Cell Integrated with Copper Interconnects,” 2002 Symposium on VLSI Circuits, Paper 12-4.
DICK JAMES is a 30-year veteran of the semiconductor industry and the senior technology analyst for Chipworks, an Ottawa, Canada-based specialty reverse engineering company that gets inside technology and takes apart ICs and electronics systems in order to provide engineering information for its customers. Contact him at 3685 Richmond Road, Suite 500, Ottawa, ON, K2H 5B7, Canada; ph 613/829-0414, fax 613/829-0515, [email protected], www.chipworks.com.