Issue



Managing defects in DRAM stack capacitors using in-line e-beam inspection


03/01/2007







The growing complexity of the stack capacitor process module is driving new electron-beam inspection applications in advanced DRAM manufacturing fabs. DRAM designers are striving to keep high cell capacitance, while increasing the memory content (i.e., number of bits) in a smaller die. As a result, the construction of the capacitor structure requires higher aspect ratio contacts, which are commonly called landing plugs and storage nodes. The narrow etch process window at these process steps adds risk of yield excursions whenever the contacts are not well formed.

Electron beam inspection (EBI), using voltage contrast capability, is employed to identify electrical failures during semiconductor processing, reduce process development cycle time, and accelerate yield learning in semiconductor manufacturing fabs. EBI provides important information on open contact excursions without having to wait for electrical test. For example, this sequence of process steps includes EBI as part of the standard 90nm node stacked capacitor DRAM process flow:

  1. Contact photo
  2. Contact etching (LPC)
  3. Contact barrier oxide deposition
  4. Contact oxide wet etching
  5. Nitride_stop_layer_removal
  6. Implant
  7. PolySi deposition
  8. PolySi CMP (LPP)
  9. EBI (including pre-anneal)

EBI has been used for a long time to detect under-etched Metal 1 contacts in memory and logic fabs. However, the very small size of the bottom of landing plugs and the use of low-conductivity filling poly materials pose new challenges to the ability to detect open contacts in a stack capacitor structure.

When this investigation started, the only detection capability for open contacts was to inspect LPP CMP wafers, which receive an extra annealing process to increase poly conductivity and therefore enable stronger voltage contrast detection. Although this method allows reacting to yield excursion faster than final e-test, it is not optimal for the following reasons:

  1. The wafers are not standard due to the extra anneal and have to be scrapped after e-beam inspection. Scrap represents significant additional cost to the manufacturing fab.
  2. The EBI is usually done a few days after the excursion occurs and a large number of wafers remain at risk.

We investigated specific inspection conditions at the LPC etch step to meet the following requirements: 1) find all critical defect types that are currently detected in LPP CMP annealed material, and 2) show strong correlation to e-beam defect maps and e-test fail bit maps.

LPP CMP inspection results

EBI on annealed LPP CMP wafers represented the baseline for our LPC inspection characterization. The baseline EBI-using an eS31 tool from KLA-Tencor-showed good correlation to electric test results, including special distributions of defects in yield maps.


Figure 1. a) Failure mode observed by DVC e-beam inspection of the wafer surface was b) confirmed to be an open contact as seen in the FIB cross-section. c) A close-up of the contact bottom where a thin residue composed of C, N, O, and Si was found.
Click here to enlarge image

In particular, perfect matching between eS31 DVC (dark voltage contrast) defect signatures and bit failures was observed. A FIB (focused ion beam) cross-section confirmed open contacts as the failure mechanism (Fig. 1). EDX elemental analysis of the material at the bottom of the contact showed a thin residue, mostly made of C, N, O, and Si. It is likely that this contamination was blocking the nitride stop layer removal, resulting in open contacts (Fig. 1c).

EBI after LPC etch

The biggest challenge with EBI at LPC is that there is no conductive material to fill the plug, such that defect detection mostly leverages material (not voltage) contrast. The LPC EBI was set up using a 35nm pixel size due to small contact opening size, as compared to the 70nm pixel applied at annealed LPP CMP. In order to maintain the same inspection throughput, a different swathing sampling strategy was implemented (12% swath sampling vs. 25%).

Two types of defects of interest (DOI) were observed on a test wafer:

  1. Material contrast (physical) defects such as polymer residue between the top of the poly gates.
  2. Voltage contrast (electrical) defects at the bottom of the contacts, caused by either incomplete contact etch or remaining barrier material.

After LPC inspection, the wafer was brought back into production up to LPP CMP. It then received the extra annealing process to reproduce the condition of standard inspection.

The same defect signature of open contacts near the wafer notch was observed after LPP inspection. However, fewer overall defects were reported, likely because the polymers might be removed by the pre-clean prior to the polysilicon deposition step.


Figure 2. Two different defects were observed by the eS31 e-beam tool, first at LPC then at LPP layers, and the same two defects were then confirmed by FIB to be open contacts.
Click here to enlarge image

Figure 2 shows a comparison of defect images from the same defect location on the LPC contact etch and LPP polysilicon CMP layers. FIB images from eS31 maps confirmed that both inspections were suitable to find open contacts.

After we confirmed that LPC inspection is capable of detecting critical defects (e.g., open contacts), we focused on applying some defect binning rules, which can increase the defects of interest (DOI) to total defect ratio.


Figure 3.LPC contact open DVC defects correlate well to LPP CMP contact open defects.
Click here to enlarge image

We applied defect size sorting to the LPC map (to show only defects >0.4mm) by using a rule-based binning (RBB) algorithm. This operation removed the polymers (not critical defects) and left only the open contact defects. The resulting map showed good defect signature correlation to the LPP map. Over 90% of the DVC (e.g., contact open) defects caught at the LPP CMP inspections were caught in the LPC etch defect pareto (Fig. 3).

E-beam inspection after LPC etch appeared to offer sufficient sensitivity and key DOIs were captured (open contacts). On the other hand, LPC inspections did not have the opportunity to detect polysilicon deposition and micro-piping defects, which were other DOIs (in addition to open contacts) that are usually monitored after LPP CMP inspection.

Summary

The LPC contact etch inspection results, with a defect size filter applied to isolate killer contact open defects, showed good spatial signature correlation to the existing LPP CMP inspection step. The main benefits of implementing e-beam inspection at the LPC etch step were time-to-results and cost savings through elimination of scrap material. By performing the inspection at the LPC contact etch step, we detected defect excursions much earlier-estimated at 2.5 days earlier-than at the LPP CMP process step. A significant cost saving was also obtained by avoiding an extra annealing process and consequent wafer scrap.

Acknowledgments

This paper was originally presented by Dr. Chi-How Hsu at the KLA-Tencor Yield Management Seminar, Hsinchu Taiwan, August 2006. The authors would like to acknowledge Tings Wang, Yen-Ming Hung, Jia-Rui Hu, and Chung-I Chang of ProMOS, as well as Debbie Hu and Mark Keefer of KLA-Tencor for their work and discussion.

Chi-How Hsu received his MS in chemical engineering from the Central U. in 1997. He is a defect control department engineer at ProMOS Technologies., No.19,Ke Ya Rd., Daya Township, Taichung County, Taiwan 428, ROC; ph 886/4-25218888-1861; fax 886/4-25218889.

Ching-Sung received his PhD in electrical engineering from the U. of Central Florida. He is with ProMOS Technologies, Hsinchu, Taiwan, working for the production technology development.

Gerry Yang received his MS in materials science from Ocean U. in Taiwan. He is e-beam products application engineer at KLA-Tencor, Taiwan.

Oreste Donzella received his BS and MS degrees in electrical engineering from the U. of Rome, Italy. He is VP of marketing and application engineering at KLA-Tencor.