Electron Devices Meeting goes 3D, low-power
02/01/2007
The 2006 International Electron Devices Meeting in San Francisco, Dec. 10, 13, may be remembered as the start of a trend toward 3D integrated circuits with stacked devices. In addition, while last year’s IEDM featured proposed advances in high performance CMOS devices, many with metal gates and high-k gate dielectrics, this year there was much more focus on optimizing future 45nm and 32nm devices, especially to achieve lower power and simplified process flows. Highlights included work on strained silicon to increase speed at lower voltage to cut operating power, novel materials for metal gates and high-k dielectrics to limit leakage power loss, and improvements in low-k dielectrics in interconnects to boost speed at lower power.
As usual, there was also a wide assortment of innovative device ideas in areas such as gene chips, nanowire devices, phase change and polymer resist memories, self-assembly schemes sometimes using DNA or proteins, and a power sheet that could sense the position of electrical devices, such as sensors or cell phones, and selectively feed wireless power to them at 13.56 MHz (reported by T. Sekitani and his group at the U. of Tokyo).
The 3D future was sketched out in a plenary talk by Chang-Gyu Hwang, president and CEO of Samsung Electronics Business Div. While multichip packages (MCPs) offer a start toward 3D and will continue to evolve, this approach faces issues with cost, repair, and redundancy, as well as performance. Meeting the challenges of stacking devices on chips to provide true 3D circuitry will be a goal of Samsung’s Fusion program, which Hwang announced in his talk.
The first device in the Fusion program was described in an IEDM presentation detailing an ultradense NAND flash memory that stacks 32-bit cells in two interconnected layers. Initial cells are built on a bulk silicon wafer, but others are then built into a thin SOI-like single-crystal silicon layer grown on top of the BEOL dielectric with a common source line through the two layers, according to Samsung presenter Soon-Moon Jung (see figure). This common source line solves a potential problem with a floating thin-body SOI scheme that allows only one cell to be erased at a time. The common source line for the cell string is tied to the body of the cell string electrically, thus allowing both cell strings to be erased in the same way, 32 bits at a time. Jung concluded that his group sees no reason that this stacking technology could not be extended to eight layers, making terabit NAND flash chips feasible using ArF lithography.
In the plenary talk, Hwang explained that 3D stacking might also be advantageous for logic. He cited the possibility of dual microprocessors being stacked, taking half the chip area. Stacking logic also might shorten interconnects and reduce parasitics, he suggested. Hierarchical stacking of memory and logic might also be feasible, followed by the stacking of RF modules, CMOS image sensors, or bio-sensors over logic and memory layers.
Expanding semiconductor capabilities will increase industry momentum, Hwang believes, as new materials, devices, and even concepts emerge. He suggested this will lead to a fusion of information technology, nanotechnology, and biotechnology for a vast new array of applications.
Novel solutions were presented to cut leakage problems in transistors as gate lengths shrink and gate dielectrics become thinner. One idea, proposed by N. Singh, et. al., of Singapore’s Institute of Microelectronics, is to surround a 3nm nanowire with the gate. Other researchers at the Institute (L. Bera, et al.) suggested stacking nanowires into multi-transistor sandwiches in a silicon-germanium nanowire array with gate-all-around (GAA) p-FETs. Another approach, presented by T. Ernst, et al., CEA-LETI, France, entailed stacking nanobeams with 10nm channels and with gates down to 80nm using GAA finFET HfO2/TiN gate stacks to improve current gains up to 6×.
The first 45nm CMOS device using ultra-high NA (1.07) immersion lithography was described by H. Nii, et al., of Toshiba. It included a number of stress enhancement techniques, including embedded SiGe, a stress memorization technique (SMT), and a dual-stress liner (DSL). The device uses porous low-k dielectric in the interconnect and incorporates SRAM with 0.25nm2 cell size. The contact holes for the ultra-dense embedded memory would have been extremely challenging with dry litho, but the 1.07 NA immersion approach enabled them to be realized with simple illumination.
While SRAM is normally used with microprocessors as an embedded cache, G. Wang and a team at IBM reported an embedded SOI-based 2-Mbit DRAM cache for 65nm microprocessors with 0.127µm2 memory cells with 1.5 nsec access time, fastest ever for embedded DRAM and only half the speed of SRAM.
Among a wide range of memory advances was a polymer resist memory, reported by B-O Cho and a group at Samsung, that proved thermally robust and easy to fabricate.
Several approaches to self-assembly were reported, some of them using DNA or proteins. Carbon nanotubes can be precisely positioned into defined circuit patterns using DNA templates in an approach described by J. Bourgoin and a group at CEA Saclay. Cage-shaped apoferritin protein molecules can transport metals or other inorganic materials into nanodots or other structures on a silicon substrate using techniques described by I. Yamashita, Matsushita.
Biological diagnostics are now being done with DNA microarrays on biochips incorporating surface-bond fluorescent tags that can be read in a reader that might cost in the range of $20,000, according to Vivek Subrananian of UCal-Berkeley. An alternate approach, reported by S-J Han and a group at Stanford U., tags biomolecules with magnetic beads so that the markers can be read by giant magnetoresistive sensors, like the heads on a disk drive, promising lower cost diagnostics. -B.H.
SRO for hungry chip techies
There were standees in several sessions as the 2006 IEDM drew a record 2030 attendees from all over the globe to witness 226 technical presentations over three days at the San Francisco Hilton. Conference organizers report that the crowd downed 354 gallons of coffee and consumed 4200 chicken wings.
Two short courses, on 32nm CMOS technology and memory technologies for 45nm and beyond, on the Sunday prior to the conference drew an unexpected 787 sign-ups. The CMOS course, organized by Ken Rim of IBM, explored major issues in moving toward 32nm half-pitch devices, including scaling problems, device architectures and performance elements, advanced gate stacks, lithography economics and technology, and interconnect (BEOL) technology. The memory course, organized by Rich Liu of Macronix, covered SRAM and embedded memory, DRAMs, NOR and NAND flash, and emerging memories. -B.H., E.K.
Mears Technologies addresses gate leakage with band engineering process
A key problem looming for semiconductor manufacturing at the 45nm node and beyond is gate leakage, as there’s no high-k/metal gate solution ready to tackle it in a manufacturing environment. However, Mears Technologies recently announced what it believes to be a solution-using band engineering to re-engineer the physical properties of silicon.
The company’s technology was developed using quantum mechanics simulations without using external assumptions, according to Robert Mears, company founder, president, and CTO, who described the solution, called MST Platform, to Solid State Technology. “We know the sorts of fields the channel will experience at the 32nm node.” The technology is an epitaxial silicon stack inserted into a standard CMOS flow, which Mears says involves no new materials and uses standard industry tooling. In addition to providing gate leakage reduction for bulk CMOS, the company says it also provides such benefits to process-induced strain and SOI applications.
Proprietary recipes were developed by the company to deposit very thin (~100Å thick) layers of epitaxial silicon. This epi stack is a channel replacement layer, and the result is that the silicon layer appears to behave more like a laminate-particularly with respect to its electronic properties, explained VP of engineering Scott Kreps. “Although it’s still single crystal silicon, it’s stratified so that there are layers in which electrons [and holes] find it easier to travel in the plane of the device, but not very easily in the vertical direction,” he said (see figure).
The company reports it has achieved gate leakage reduction of up to 70% in NMOS transistors and up to a 90% reduction in gate leakage for PMOS transistors, while maintaining drive current. Kreps said that the company has proven its technology at the 130nm node and demonstrated it at the 90nm node, having built “dozens of fully integrated device runs,” and “produced over 1000 wafers of epitaxial deposited films.” He added that although the first couple of customer implementations are likely to be at the 45nm high-performance node, where gate leakage is the overriding issue, the company sees no barriers to scaling the technology even beyond the 22nm node. Mears’ solution is also backwards applicable to 65nm, he noted.
Many IDMs and foundries may have already selected their tools and are nearing completion of their 45nm process development, but Kreps insists that there is still quite a bit of flux in terms of what people will do for the high-performance node. “The low-power node generally comes out first and is fairly well set for many companies,” he said, but added that companies in talks with Mears have indicated that “there are some unresolved issues for the 45nm high-performance node.” -D.V.
ASML illuminates a dry path to 40nm
The International Technology Roadmap for Semiconductors plots a route to 45nm half-pitch through water immersion lithography for critical levels, but ASML is giving its customers an alternative by request-one that employs familiar dry DUV exposure and the double pattern method being considered for 32nm.
The company’s XT:1450G, a version of its familiar 0.93NA Twinscan system expected to be available in 2H07, is speced to print 143 wafers/hour at 40nm double-patterning resolution. Of course, there is a trick-the wafers must be sent through the exposure tool twice, each time printing one of two >80nm half-pitch patterns. Getting the 4nm overlay required for the summed geometry means making sure that the wafer sits in the same chuck during both exposures. If the chuck selection is random, the overlay spec goes to 6nm, reports Bill Arnold, chief scientist of ASML. If only one chuck is being used, the throughput drops to 65 wph/pass.
This double patterning scheme requires that the wafer be processed between exposures to develop the resist and transfer the first image into a hard mask layer. Thus, the actual throughput of finished wafer layers will be <143 wph, but probably not much less than ~70 wph for optimized processes.
Such optimization would be appropriate for chips made in long production runs, such as flash memories, and the geometries used in flash may be less sensitive to the kind of errors that might occur in double patterning. The 4nm chuck integrity spec, for example, is quite adequate for layer-to-layer overlay, but consumes all of the 10% CD uniformity spec for a 40nm design. If double patterning is to be successful, gates and other structures to which a 4nm CD spec applies will have to be printed entirely in a single exposure. While 70 wph throughput (for finished wafers) may seem slow compared with immersion lithography tools designed to print 45nm chips in a single exposure, the tool cost and operating expenses are likely to be lower as well.
The critical difference in cost-of-owner-ship may come down to mask costs. While one might expect that the two reticles needed to print a layer by double patterning would cost more than a single mask used for immersion, the total number of printable features will be the same. That means that the immersion-capable reticle will take about as long to write, inspect, and repair as both the double patterning reticles together. Since the k1 factor for immersion at 45nm half-pitch will be ~0.31 for immersion (at NA=1.35), vs. the XT:1450G operating at k1~0.43 with double patterning, the yield of the immersion-capable reticles is likely to be lower and require more challenging OPC schemes. The net effect is that reticle costs may actually be lower for the double patterning method. -M.D.L.