Issue

Change and silicon: the only constants

02/01/2007

They say that the only constant in the integrated circuit industry is change. Every two years, Moore’s Law brings another technology generation. Even more often, consumer requirements force manufacturers to improve their designs or risk falling behind. The last decade alone brought immersion lithography, low-k interconnect dielectrics, copper wiring, aggressive resolution enhancements, and commercial use of silicon-on-insulator (SOI) wafers. Looking back 50 years, we would expect the manufacturing process to be completely unrecognizable.

Certainly it’s hard to see any resemblance to today’s integrated circuits in that first Bell Laboratories transistor. Clumsily three-dimensional, it looks like the hand-wired laboratory experiment it was. It depends on germanium, a high mobility semiconductor that, even now, suffers from poor surface quality and poor device reliability. The wiring is functional, but how could you ever maneuver these discrete, self-supporting wires through the contortions required by even crude circuits? That first transistor was certainly a leap forward from the vacuum tube-although the vacuum tubes of the time were more reliable-but few could have imagined it would evolve into today’s inexpensive, high-performance integrated circuits.

Figure 1. Monolithic integrated circuit, built at Fairchild Semiconductor in 1961. (Image courtesy of Fairchild)Click here to enlarge image

Yet just 14 years later, in 1961, we find in Robert Noyce’s integrated circuit design clear foreshadowing of more modern devices (Fig. 1). The substrate is silicon. The wiring is aluminum, and planar. The lines are the neat polygons of mask-based photolithography. The transistors are bipolar-MOS transistors were still further down the road-but they lie neatly in the plane of the substrate. An engineer familiar with the Noyce device could be forgiven for thinking that today’s integrated circuits differ primarily in scale.

The most obvious link between the past and present is silicon itself. Silicon, sometimes described as God’s gift to electrical engineers, is readily available, the most common metal in the Earth’s crust. It offers usable mobilities for electrons and holes, making complementary logic possible. Most of all, it oxidizes to form silicon dioxide (SiO2). A stable, self-limiting oxide, about 23Å thick, forms naturally on any silicon surface exposed to air. The oxide passivates and protects the surface, securing it against corrosion and many forms of contamination. It’s a good insulator, too, suitable for isolating devices from each other and creating capacitors within devices. While every other semiconductor requires careful surface and interface engineering to avoid electrical defects and ensure functional devices, the silicon/SiO2 interface has stable, predictable electrical characteristics. This interface is a leading reason why silicon quickly surpassed germanium as the semiconductor industry’s material of choice, and why silicon dominates IC manufacturing to this day.

Silicon wafer manufacturing

Look closer at silicon’s longevity, though, and you’ll see a lot of change. Wafers have grown from diameters of an inch or less to today’s 12-inch platters. Along the way, almost every aspect of wafer manufacturing has improved, from the polysilicon purification process to wafer manufacturing.

The so-called Siemens process purifies metallic silicon by reacting it with HCl to make trichlorosilane (TCS, HSiCl3) and other chlorosilane compounds, distilling impurities out of the chlorosilane, and finally reducing the chlorosilane in hydrogen to deposit ultrapure polysilicon. As Gary Homan, VP and director of marketing and sales at Hemlock Semiconductor explained, the procedure is now a nearly perfect closed loop: the chlorine evolved during polysilicon deposition is recycled back into the process to help make the next batch of chlorosilane. Originally, the byproducts of polysilicon manufacture were sold to other industries. Now, Homan said, 99% of these byproducts are recovered and reused. Chemical reuse, which depends on cost-effective methods for re-purifying the byproducts to electronics grade, dramatically reduces both the cost and environmental impact of polysilicon manufacturing.

The distillation and re-deposition processes have also improved, largely due to the introduction of metal reactor vessels in place of quartz. Metal can withstand much higher pressures, which, in turn, can support faster reaction rates and higher manufacturing throughput. Homan believes that today’s enormous silicon volume-Hemlock Semiconductor alone manufactures more than 30,000 tons per year-would be neither economically feasible, nor perhaps achievable, with quartz reactors.

To transform polysilicon chunks into single crystal silicon wafers, manufacturers turn to the Czochralski (CZ) growth process, another industry constant. CZ growth lowers a seed crystal into a quartz crucible filled with molten silicon. Gradually pulling the seed out allows the silicon to cool around it, using the seed as a template for a crystalline ingot. Uneven cooling causes thermal stress, leading to dislocations and other defects. Since a larger diameter ingot has less surface area compared to its volume, maintaining uniform cooling was a major challenge in the transition from 2-inch to 3-inch wafers, and remains a challenge as manufacturers transition to 300mm wafers and beyond.

The drive to larger wafer sizes is another industry constant, as they have always offered a competitive advantage. According to Siltec founder Bob Lorenzini, IBM was known for insisting on wafers larger than anyone else’s. In 1969, when Siltec was founded, the industry standard was two inches, but IBM’s wafers were two and a quarter inches in diameter. While the development of a common wafer size standard hasn’t made the technical challenges any easier, it has helped wafer suppliers receive an adequate return on their investment in larger crucibles and crystal pullers. Still the necessary investments get larger as the wafer size increases. The industry is now beginning to explore a possible transition to 450mm wafers, even though wafer and equipment suppliers are only starting to recoup their 300mm investments. SEMI President and CEO Stan Myers warned that equipment suppliers, having funded the 300mm transition, are especially wary about switching again so soon.

To buy or not to buy?

The evolution of independent wafer and equipment suppliers is one of the most significant changes since the semiconductor industry’s early days. The very first manufacturers-companies like Fairchild, Texas Instruments, and IBM-had little choice but to grow their own silicon wafers. Few commercial suppliers could meet the purity requirements of electronics grade silicon. Yet by the 1970s, second-generation manufacturers like Intel and AMD felt that the silicon infrastructure was mature enough to supply their needs.

Wafer manufacturing has changed in ways beyond the wafer size. For instance, oxygen impurities are unavoidable: the growing crystal traps oxygen from the air around it, and even consumes part of the quartz crucible itself. Trapped oxygen forms SiO2 precipitates. If these precipitates are too large, or clustered in a particular region, they can interfere with device performance. Once manufacturers learned to control them, however, oxide precipitates became a vital tool for contamination control: they trap, or getter, metallic impurities scattered throughout the growing ingot. The introduction of epitaxial silicon-a silicon layer vapor-deposited on top of the original wafer-helped make sure that oxide precipitates in the wafer bulk would not interfere with devices on the active device surface.

Low-temperature epitaxial deposition of silicon depends on silane (SiH4), an unstable, pyrophoric compound. According to Applied Materials founder Michael McNeilly, one of the first challenges for the company was to prove that its epitaxial reactors could handle silane safely. In fact, the company’s first product was a silane gas panel. Early on, Applied Materials built a small silane plant in East Palo Alto for demonstration purposes. When confronted with liquid nitrogen dewars containing pure liquid silane, McNeilly said, visitors generally either fled or started placing equipment orders.

While silane is an extreme example, many chemicals used in semiconductor manufacturing are hazardous. In some cases, engineers either weren’t aware of the risks or chose to ignore them in the rush to get production of new devices up and running. Myers observed that people don’t wash their hands with trichloroethane (TCE, a known liver toxin) any more, for example. In other situations, the hazardous nature of chemicals like hydrofluoric acid indirectly helped improve process performance: an engineer wearing a protective chemical suit was unlikely to contaminate the devices.

Wafer surface engineering has recently come to the fore again. SOI devices have historically been relegated to military and aerospace circuits and other radiation-hardened applications. Yet the buried oxide layer also helps reduce parasitic capacitances and improves isolation between adjacent transistors. IBM and AMD, among others, have both adopted the technology for their microprocessors. Even more recently, germanium has reappeared in transistor manufacturing. Though the channel still depends on silicon, advanced devices use SiGe source and drain regions to apply strain, increasing carrier mobility. Even further down the road, researchers at the Belgian research institute IMEC and elsewhere have demonstrated germanium channel PMOS transistors with nearly triple the mobility of silicon. NMOS transistors are more difficult, IMEC fellow Marc Heyns conceded, but might be possible with GaAs on a Ge substrate (see “Turning to an old friend, engineers are re-considering germanium,” p. 33).

The use of silicon and SiO2 defines many other process features, too. For example, the band gap of a semiconductor defines the appropriate dopants for both p-type and n-type materials. Once silicon was chosen as the starting material, doping with boron and phosphorus was inevitable. Still, for most of the early history of IC manufacturing, dopants were diffused, not implanted, by annealing silicon wafers along with a sample of the desired dopant material. Needless to say, this method makes precise dose and location control difficult. Ion implantation was first used to make semiconductor devices in 1966, at Hughes Research Laboratory. But the technique only began to take off in 1970, when Texas Instruments demonstrated that ion implanted devices could achieve far superior threshold voltage control. In 1971, Extrion became the first company to build commercial implanters specifically for IC manufacturing.

Enter the MOSFET

The planar MOSFET, the heart of a modern integrated circuit, was actually one of the last pieces to fall into place. Early transistors, following the vacuum tube model, placed collector, base, and emitter regions adjacent to each other, connecting each region to a terminal. The p-n-p (or n-p-n) doping of these regions created two p-n junctions; changing the bias of the base electrode opened or closed the resulting switch.

The mesa process originally used to make these devices etched pillars out of the silicon (or germanium) wafer, then connected wires threaded through tiny capillary tubes (the ancestors of today’s wire bonders). This approach worked, although, according to Micronix co-founder Sam Harrell, 5% yield for Texas Instruments’ early integrated circuits was considered good. But integrating multiple transistors on a single substrate called for a monolithic, batch-oriented process. In a planar process on silicon, manufacturers could begin by oxidizing the entire wafer-passivating and protecting the surface-only opening “windows” in the oxide where they were needed for dopant diffusion or electrical connections.

Julius Lilienfeld proposed the MOS transistor as far back as 1925, but it was only realized in 1963. It uses a capacitor, rather than a direct connection, to switch the current in the channel. Thus, the MOSFET exploits silicon’s excellent oxide, using it as the dielectric of the gate capacitor. The oxide protects the underlying silicon, while the capacitor makes a direct electrical connection to the channel unnecessary. Moreover, MOSFETs, unlike junction transistors, depend on the flow of majority carriers. With more carriers available, they are less sensitive to thermal fluctuations and other sources of noise. Still, implementation of reliable MOS ICs depended on two key insights. The first was the realization by Fairchild Semiconductor that sodium contamination made transistors unstable. The second was the discovery at RCA that annealing in hydrogen eliminated traps at the silicon/oxide interface. History does not record how the two insights merged into a single design. According to legend, engineers from both companies were present in a Las Vegas swimming pool in 1965, during the first IEEE Silicon Interface Specialist Conference. All concerned adamantly denied sharing proprietary information, much less engaging in anticompetitive collaboration. Yet, certain key phrases wafted through the air, and within weeks, both companies began to deliver reliable MOS-based integrated circuits.

Figure 2. Cross-section of 64-bit high-performance microprocessor chip. (Image courtesy of IBM)Click here to enlarge image

More than 40 years later, though channels are smaller, oxides are thinner, and devices with two or more gates are appearing on technology roadmaps, the basic MOS device remains the foundation of almost all integrated circuits. Proposed new devices are judged by their MOS compatibility first, and all other capabilities second. Though the wiring is now copper, rather than aluminum, and the transistors are nearly invisible under towering networks of lines and vias (see Fig. 2), today’s circuits still carry the DNA of their illustrious ancestor.

Change and silicon: the only constants

Silicon wafer manufacturing

To buy or not to buy?

Enter the MOSFET

Further reading