Integrating photonics: Hitachi, Oki put LEDs on silicon
01/01/2007
Hitachi Ltd.’s central research laboratory reports making a light-emitting diode (LED) from ultrathin silicon thin film with conventional CMOS technology, a step toward potentially putting high-speed optical connections on conventional low-cost silicon devices, without the issues of integrating compound semiconductor materials with standard silicon, reports SST partner Nikkei Microdevices.
In a slightly more mundane but actually available solution, Oki Electric Industry Co. Ltd. is selling a small color printer that uses LEDs made by bonding light-emitting GaAs layers onto silicon circuitry with a layer transfer process.
Hitachi researchers got light emission at wavelengths of 800nm-1µm from a silicon thin-film pn junction on a silicon-on-insulator (SOI) wafer (see figure). Researchers used local oxidation of silicon to isolate a very thin section of the single crystal silicon layer on the SOI substrate, making a layer as thin as 9nm without degrading its crystal quality. The nanoscale film acts as a quasi-direct band-gap semiconductor, thanks to the quantum mechanical confinement effect. Injecting current into the 2D quantum well produces electroluminescence.
The company is next working to develop the related technologies needed to use the silicon thin-film emitter for on-chip optical connections, including confirming transmission at gigahertz speeds, confining the light in the desired pathway without scattering, and improving conversion efficiency beyond its current 1%. Researchers say they hope to make a silicon thin-film laser diode within one to two years.
Meanwhile, Oki Electric and its subsidiary Oki Data have moved beyond the R&D stage and are integrating GaAs LEDs directly into silicon chips in commercial products, used in their small C3400n digital LED printer, which sells for $400-$500. The companies essentially etch the light emitting layer off the GaAs substrate, bond it on to CMOS circuits using low temperature epitaxial film bonding, and then continue making the interconnect layers, integrating the LED with its driver circuits on one chip.
Because the bonded-in LED unit is so much more compact without the need for its own external connections, company officials say they can get 5-10× more LED arrays from each GaAs wafer.
Oki first puts a sacrificial layer of AlAs on the GaAs wafer, then grows a 2µm light-emitting layer using metal organic vapor phase epitaxy. Next, 60µm × 8.1mm blocks are etched out of this light emitting layer on the GaAs wafer, matching the pitch of the circuits on the silicon wafer. The etched out pattern of light-emitting film is covered with a sheet of adhesive, and then the sheet is peeled off, removing the block pattern of light emitter film all arrayed in position. The silicon wafer with the driver circuits is coated with a reflective layer of Ti and covered with polyimide to make a flat surface. The sheet of patterned light-emitter film is applied to the patterned silicon, where it attaches by molecular forces. The adhesive sheet is then removed, and the wafer annealed at 300°C for an hour to strengthen the bond. This transferred layer is then etched into LEDs, and CMOS interconnect layers added on top.
The company claims yields approach 100%, though it is using only 100mm GaAs wafers and 150mm Si wafers. It says the LEDs across the chip vary in light emittance by +/- 7%, but that on-chip controls can correct that to +/-1% variation. At 0.6mA there was 1.5% change in brightness after 100 hours.
The light-emitting layer can also be transferred to glass, where it may have potential for displays. -P.D.
SEZ adds serious tricks to single-wafer spinner for FEOL
After 20 years of supplying single-wafer wet-processing systems, SEZ has released a new mass-production tool capable of performing extremely complex processes for front-end-of-line (FEOL) applications. The new Esanti tool combines with the DaVinci back-end-of-line (BEOL) tool such that SEZ can now address 60% of the total wet processing market.
The former Bernoulli chuck with edge-pins has been replaced with a new chuck where the edge-pins do all of the wafer holding and maintain a greater spacing to the chuck bottom. In so doing, the chuck allows chemical media to be dispensed onto the backside.
SEZ’s DaVinci tool for BEOL applications added double-sided processes capability earlier this year. Esanti is also double-sided capable, but separates out the chemical handling unit, with point-of-use heating, and three media in one chamber and four media in the whole tool. For example, one single-wafer chamber can handle enhanced sulfuric acid (ESA), standard clean 1 (SCI), and then a solvent.
An “Active-Jet” of liquid droplets has been added to assist in particle removal. The kinetic energy of N2 gas is used to generate and accelerate droplets of water toward the wafer surface. “We’ve looked at cryo and these other technologies, and they all have advantages and drawbacks,” explained Leo Archer, SEZ VP of emerging technologies worldwide. “The single-biggest driver for customers is zero damage.”
The new tool also includes an atmospheric surface drying (ASD) wand, which dispenses IPA vapor mixed with N2 gas to create a linear Marangoni force for drying. SEZ reports very good results, even with 50:1 or 60:1 aspect ratio DRAM structures. The Marangoni principle has been around for many years, but prior implementations relied upon chamber walls for isolation. The ASD wand functions in an open atmospheric chamber over a spinning wafer, moving in parallel with the DI dispense to prevent watermarks and pattern collapse. Much of the development work for ASD was done in SEZ’s Japanese lab.
A fully configured eight-chamber system with an optimized process is capable of delivering up to 250 wafers/hour. The single-wafer wet processing system is also available in a four-chamber design.
Archer noted that SEZ has had single-chamber Esanti alpha-tools at customers for several months working on ESA and several full-beta tools at customers, and the company has received its first order, scheduled to ship in 2Q07. -E.K.
Stitching up the rift between design intent and manufacturing
Founded in January 2003, software start-up Aprio has been attacking the DFM challenges facing IC manufacturers at advanced technology nodes with a product line that it says enables users to inject manufacturing intelligence into existing design tools.
El Dorado Ventures and Mobius Venture Capital are majority investors in the company, with minority stakes from Goldman Sachs and KT Venture Group, the investing arm of KLA-Tencor (which is also a development partner).
Because traditional DFM tools require that RET must be applied to the complete mask layer all at once, if a mask layer has to be reprocessed because of errors, the entire process has to be repeated, Gianfagna explained to SST. Aprio’s technology provides the ability to apply different OPC rules to different parts of a mask layer, and then stitches the parts together, healing the boundaries between the pieces of the mask. The end result appears to be monolithically built even though it was actually created using multiple OPC strategies over multiple runs. Gianfagna says that the “secret sauce” is in the algorithms that enable the stitching and healing.
The company’s range of products includes Halo-Quest-which predicts what a layout will look like in silicon and identifies errors-as well as Halo-OPC/Halo-iOPC, and Halo-Fix. -D.V.
New ZRAM 10× better in tests at 65nm and 45nm nodes
Innovative Silicon Inc. (ISI), a developer of silicon-on-insulator (SOI) memory cell IP, has released a Gen2 version of its zero-capacitor floating-body “ZRAM” technology, based on a standard SOI logic process with a similar one-transistor bit-cell. The new technology “results in much more charge being stored,” said Pierre Fazan, chairman and CTO for ISI, explaining that Gen2 “provides a greater programming window, with trade-offs between speed, power, and density possible for different applications.”
The bitcell layout and the peripheral circuits are different, so mask-sets change between Gen1 and Gen2. Since Gen2 provides greater value, ISI expects to get paid for this greater value-and current Gen1 contracts don’t automatically turn into Gen2 contracts.
AMD is one company happy with its conversion to Gen2. “We are very excited about Z-RAM Gen2. The combination of density, power, and performance coupled with its ability to work with our standard manufacturing processes makes it an extremely attractive option for use in our future microprocessors,” particularly for larger on-chip microprocessor caches, said Craig Sander, corporate VP of technology development.
ISI thinks that ZRAM can cover most of the embedded memory space except for that currently served by ultrahigh-speed SRAM, and the ultralow-power market including battery-based applications such as pacemakers. “There are other floating-body memory devices out there, but all of the others are similar to our Gen1. There’s nothing else out there like our Gen2 in how we generate and read the charges,” Fazan stated.
Since the industry is expected to move to fully depleted SOI and/or multigate FET designs, ISI has tested the new Gen2 structures work with both of these future approaches. Silicon-validated macro at 90nm, test chips in multiple fabs at 65nm and 45nm nodes, and the bitcell have been validated on an additional five processes. And, hinted Jeff Lewis, ISI VP of marketing, “AMD may not be the first company in production with it. -E.K.
Scientists mull new state of matter for semis
A trio of Stanford physicists say they’ve found a way to create a new state of matter possessing “extraordinary” properties for semiconductors, including less energy dissipation and less heat generation.
The work is based on the quantum Hall effect, already the basis for two Nobel prizes (1985 and 1998), which describes electrical current flow at the edges of two-dimensional electron systems (e.g., sheets of semiconductor materials sandwiching a layer of electron gas) that are subjected to a high magnetic field and ultracold temperatures-conditions that are incompatible with conventional semiconductors.
However, in their new research (published in the Dec. 15 issue of Science), the Stanford scientists say a new state called “the quantum spin Hall effect” could be realized without an external magnetic field. Stacking and skewing alternating layers of mercury telluride and cadmium telluride, they created a crystal lattice structure similar to that of silicon or gallium arsenide. Controlling the thickness of wells in the mercury telluride, they claim, results in a phase transition into a new state of matter that can carry electric currents without any doping, so that electrical current flows only at the edges of the sample, according to Prof. Shoucheng Zhang, who led the work with two students. Electron flow typically isn’t scattered by impurities, so there would be far less energy dissipation or heat generation compared to conventional semiconductors, he explained.
Quantum wells in mercury telluride/cadmium telluride sheets can be readily fabricated, and the U. of Wurzburg in Germany is testing the Stanford group’s predictions. The research is being funded by the Microelectronics Advanced Research Corp., a US industry consortium. -J.M.