Cost, production, and logistics implications of C4NP solder bumping
01/01/2007
The newest generation of bumping technology, called Controlled Collapse Chip Connection: New Process (C4NP), works with lead-free solder alloys. The new process separates the underbump metallization (UBM) deposition from the solder bump deposition, unlike the old process integrating the two. As separated, the UBM may be more easily integrated with redistribution-layer (RDL) metal, and may be done by the wafer fab. Costs are saved by working with pure solder and relatively simpler capital equipment compared to prior approaches.
High-end microelectronic packaging is rapidly moving from wire bonding to solder bumping as the preferred method of interconnection. The various solder bumping technologies used in volume production include electroplating, solder paste printing, evaporation, and the direct attach of preformed solder spheres. Each of these established bumping technologies has important limitations for fine-pitch lead-free solder alloys. The most commonly used method of generating fine-pitch solder bumps is by electroplating the solder. This process is difficult to control and costly, especially for lead-free solder alloys. These challenges in the transition to lead-free solder bumping has led the European Union to grant exemptions from the ban of lead in certain solder bumping applications. However, the pressure to move to lead-free continues for the entire industry.
C4NP, a solder bumping technology developed by IBM and commercialized by Suss MicroTec, enables fine-pitch bumping using lead-free solder alloys. C4NP is a solder transfer technology by which molten solder is injected into prefabricated and reusable glass templates/molds (Fig. 1). The filled mold is inspected prior to solder transfer to the wafer to ensure high yields. Filled mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step. C4NP technology offers the same alloy selection flexibility as solder paste printing. It can be used for fine-pitch flip-chip-in-package and wafer-level chip scale package bumping applications.
 Figure 1. Schematic cross-section, not to scale, of mold cavities being filled with solder. |
A cost model has been developed to compare the cost of C4NP wafer bumping with alternative technologies such as electroplating or screen printing of solder. This paper will review the input attributes considered in this cost model.
Cost considerations
When comparing the cost effectiveness of different wafer bumping technologies, many factors need to be taken into account. These factors can be grouped into two categories: global factors that apply to any bumping technology and unique factors specific to a particular bumping technology.
Each of these factors directly influences the per-wafer bumping cost. In general, for a “green field” bumping installation, the cost model shows a 10-30% reduction in wafer bumping costs by using C4NP instead of electroplating.
In particular, materials cost and building overhead reap the largest percentage reduction by using C4NP instead of electroplating. This is because of the reduced footprint, chemical distribution, and waste costs of C4NP over electroplating. The electroplating process also has other factors that add to cost, including chemistry mix stations and pumping, analytical equipment, and waste treatment. Also, pure solder is used for C4NP, and not converted to a paste or plating chemistry format, which increases cost. Solder consumption is efficient since it is deposited only in the mold cavities and not wasted on plating thieves.
Production, logistics implications
When electroplating is used for wafer bumping, the solder deposition on the wafer is an integral part of the UBM formation process. First, the UBM metallurgy is deposited in a blanket format on the wafer. Next, photoresist is deposited, imaged, and developed to form openings for subsequent solder electroplating. After plating, the photoresist is stripped and the UBM metallurgy is etched, using the solder as the etch mask. Finally, the solder is reflowed and the wafer is cleaned prior to dicing and subsequent packaging operations. Since the solder is electroplated, a commoning layer is required. The UBM metal is used for this purpose, and the solder deposition cannot be separated from the UBM formation.
 Figure 2. C4NP process flow showing UBM deposition separate from solder bump formation. |
Because the process flow for C4NP is different in that the UBM pattern is formed first, and the solder deposition is the last operation (Fig. 2), this process flow provides unique production and logistics opportunities. First, the UBM formation can now be done in the semiconductor fab. Installing typical UBM photolithography equipment such as a proximity mask aligner and a coat/develop cluster in the fab is straightforward because of the already existing litho-compatible cleanroom environment. Other equipment needed for the metal deposition is often already available in the fab, eliminating the need for dedicated capital equipment.
Second, wafer-level test can be moved directly after the UBM formation step, with two benefits. First, test feedback to the fab is more immediate, which is critical in today’s rapid development cycle environment. This allows either faster development cycle times, or more cycles of learning in a given time period. The other benefit of moving wafer-level test after UBM formation is that the solder bumping step can now be moved outside of the fab location. Soldering is completely independent of wafer/UBM fabrication. Bumping can be done in the location that provides the best logistics, cost, quality, and is closest to the final packaging facility or the end user.
 Figure 3. Detailed steps for the solder transfer step within the C4NP process flow. |
Another advantage of C4NP is reduced cycle time for wafer bumping. Mold fabrication and solder filling of the mold cavities can be done as soon as the bump pattern design for a wafer is finalized. Molds can be filled and ready for solder transfer to the wafer while the wafers are still in the fab. There is not a concern with oxidation of the solder in the molds. Solder filled molds have been allowed to sit for up to a year waiting for wafers, and the solder transfer has been flawless. This is because there is a reducing gas environment at the C4NP solder transfer step, which effectively removes oxides from the solder and UBM pad (Fig. 3). With C4NP, the only operation the wafer sees is the solder transfer process, so the time required for bumping is reduced compared to other bumping processes. Also, since no liquid flux is used, there is no need to clean wafers after bumping. Another cycle time saving feature is that there is no separate solder reflow step. Solder reflow occurs in the solder transfer tool, which further reduces cycle time.
C4NP allows compatibility with applications that require thinned wafers. Wafer thinning can be performed after UBM formation. Solder transfer is the only operation after UBM formation, and there are special chucks available for handling thinned wafers at that step. Since this is the only step after thinning, the potential for damage from handling thinned wafers is minimized.
Conclusion
C4NP provides business advantages in addition to numerous technical advancements. The technology is cost effective because it is efficient in materials and space usage. Because the solder bumping is separated from the UBM formation, production, logistics, and cycle time advantages are realized.
Acknowledgments
The authors would like to thank the teams at IBM and Suss MicroTec, specifically the published and unpublished work of Peter Gruber and Da-Yuan Shih, IBM T.J. Watson Research Center, Yorktown, NY; Luc Belanger, Guy Brouillette, David Danovitch, Jean-Luc Landreville, Valerie Oberson, and Michel Turgeon, IBM Microelectronics, Bromont, Canada; Barry Hochlowski, Richard Levine, David Naugle, James Busby, and Chris Tessler, IBM Microelectronics, East Fishkill, NY; and Jeffrey Friot, Suss MicroTec.
References
- J. Lau, Low-cost Flip-chip Technologies, McGraw-Hill Book, New York, Ch. 2, pp. 43-94, 2000.
- P.A. Gruber, et al., “Low-cost Wafer Bumping,” IBM J. Res. & Dev., Vol. 49 No. 4/5, July/September 2005.
- B. Hochlowski, D. Naugle, P.A. Gruber, “Low-cost Wafer Bumping Using C4NP,” Future Fab, January 2005.
- Unpublished report, IBM Systems and Technology Group, Dr. R. Levine, Presentation in Asia, September 2005.
- K. Ruhmer et al., “C4NP: New Solder Bumping Technology: Low-cost and Lead-free,” IMAPS Flip-Chip Advanced Technology Workshop, Austin, TX, June 2005.
- D. Danovitch, P.A. Gruber et al., “IMS-Injection Molded Soldering,” IMAPS 2000.
- P.A. Gruber, D.Y. Shih et al., “Injection Molded Solder Technology for Pb-Free Wafer Bumping,” ECTC 2004.
- K. Ruhmer et al., “C4NP: Lead-Free and Low-Cost Solder Bumping Technology for Flip-Chip and WLCSP,” PanPacific Conference, 2006.
Eric Laine received his BS in chemical engineering from Michigan Technological U. and his MS in advanced technology from Binghamton U. He is a technology specialist for C4NP at SUSS MicroTec Inc., 228 SUSS Drive, Waterbury Center, VT 05677-0157; ph 802/272.4851, e-mail [email protected].
Klaus Ruhmer received his BS in electronics and telecommunications technology from the Technical College in Steyr, Austria. He has global sales & marketing responsibility for C4NP wafer bumping technology at SUSS MicroTec.