Native oxide removal for NiSi formation using remote plasma preclean
01/01/2007
In situ NF3/NH3 remote plasma preclean enables NiSi integration in SOC devices. This new preclean technology allows reliable, production-worthy integration of NiSi for CMOS technology without plasma damage or queue-time control problems. The process has been validated using integration data, such as junction leakage and sheet resistance for Ni silicide, and has been compared with conventional HF wet clean and Ar sputter preclean processes.
NiSi is one of the most suitable silicide materials for source, drain, and gate contacts in CMOS fabrication because it has low Si consumption, reduced linewidth sensitivity, and low sheet resistance [1, 2]. The Si surface before Ni deposition must be clean to ensure low defect NiSi formation and achieve low contact resistance and low leakage. The conventional cleaning methods are HF wet clean, in situ Ar sputter preclean, or a combination of the two processes. HF wet clean is ex situ to the Ni deposition process and thus has queue-time issues. Additionally, Ar sputter preclean can cause changes in device geometries and induce plasma damage in the sensitive transistor structures, which becomes more problematic as device geometries shrink. We introduce a new process for in situ native oxide removal using NF3/NH3 remote plasma, a preclean process that largely eliminates such issues.
The reactions for this process are as follows and have been widely reported [3, 4]:
Etchant generation:
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Etch process:
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Sublimation (heat treatment) process:
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The equipment evaluated for this paper is capable of both etch and sublimation processes in a single chamber as shown in Fig. 1; thus, this is a two-step, single-chamber process. The first step etches the native SiO2 present on the Si surface using the gaseous by-products of remotely plasma reacted NF3 and NH3 gases. The reaction forms a volatile by-product comprised of (NH4)2SiF6 on the wafer surface. During the second step, a heat treatment sublimates the by-product and exposes the Si surface. After heat treatment, the wafer with the clean Si surface is transferred to the Ni deposition chamber under high vacuum. The integration of the preclean chamber with the Ni chamber on the same tool is key to successful NiSi formation [5].
High SiO2:Si3N4 and SiO2:Si etch selectivities are critical, since it is undesirable to etch either Si (source, drain, and gate) or Si3N4 (gate spacer) during the native SiO2 etch. The Si etch amount for a single recipe is near zero, while SiO2 etches ~100Å. Therefore, it can be considered that the etch selectivity of SiO2:Si is nearly infinite. It is clear that the removal of native oxide will occur without measurable etching of the Si substrate under the native oxide. SiO2:Si3N4 selectivity was consistently >10 over a 3000-wafer extended run using Si3N4 deposited by LPCVD.
Process qualification
Electrical test results using 65nm node structures were used to compare the NF3/NH3 remote plasma preclean with conventional HF wet clean and Ar sputter preclean approaches. Following HF wet clean, deposition was performed on 300mm wafers in a high vacuum cluster tool with the following sequence: 1) NF3/NH3 remote plasma preclean, Ar sputter preclean, or HF wet clean, 2) PVD Ni deposition, and 3) PVD TiN deposition. PVD Ni thickness was optimized based on electric test results altering Ni thickness and set at 12.5nm. The silicidation process used first RTP anneal temperature optimized by transformation curve test results. The experimental conditions are portrayed in Table 1. Respective etching amount and film thickness were qualified on 1000Å thermal oxide.
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Sheet resistance results were similar over the 3-9nm NF3/NH3 remote plasma preclean etch range, but junction leakage results were inconsistent. Although NF3/NH3 remote plasma preclean has high etch selectivity for Si and Si3N4 films, the STI in this test was made of silicon oxide, and therefore increased etch amounts resulted in more etching of the STI. The NiSi layer formed at the depressed STI area causes higher junction leakage. Based on these results, the NF3/NH3 remote plasma preclean etching amount was set at 6nm for the succeeding electric test.
Figure 2 shows sheet resistance and junction leakage results comparing NF3/NH3 remote plasma preclean, HF wet clean, and Ar sputter preclean. As can be seen, sheet resistance results were similar on both N+ and P+ areas with all three cleaning methods, but junction leakage results are dramatically improved by NF3/NH3 remote plasma preclean and HF wet clean compared to Ar sputter preclean. The cause of high junction leakage with Ar sputter preclean would be deformation of the device structure and/or plasma damage by Ar ion sputtering. To investigate the NF3/NH3 remote plasma preclean etch property, the surface roughness and TEM cross-section at the NiSi interlayer were studied and compared with HF wet clean.
A surface roughness comparison is shown in Table 2. Thermal oxide roughness was measured by AFM, then etched by either NF3/NH3 remote plasma preclean or HF wet clean, and then roughness was re-measured. Additionally, NiSi samples were prepared on bare Si after each etch process. The NiSi was formed by the following sequence: 1) NF3/NH3 remote plasma preclean (10nm) or HF wet clean (10nm), 2) PVD Ni 10nm deposition, 3) PVD TiN 10nm deposition, 4) RTP 450°C for 30 sec, and 5) TiN and unreacted Ni strip. Table 2 shows that Rms and Ra values were almost the same. The interfaces between Si and the NiSi films were observed by TEM and were smooth and defect free for both preclean methods. The conditions of the interfaces correlate well with the electrical test results.
Queue-time study for HF wet clean
Based on the above studies, the properties of both NF3/NH3 remote plasma preclean and HF wet clean processes are very similar in terms of sheet resistance, junction leakage, surface roughness, and TEM cross-section results. However, as HF wet clean is an ex situ process, it requires tight queue-time control before Ni deposition to maintain low sheet resistance. Figure 3 shows queue-time after HF wet clean, altering NiSi sheet resistance results.
The process steps were as follows: 1) NF3/NH3 remote plasma preclean (10nm) or HF wet clean (5nm), 2) PVD Ni 10nm deposition, 3) PVD TiN 10nm deposition, 4) 1st RTP 300°C for 30 sec, 5) strip unreacted Ni and TiN film, and 6) 2nd RTP 450°C for 30 sec. The TEG wafers for this test were 90nm node. As can be seen, the sheet resistance results with HF wet clean became worse with longer queue-time due to native oxide regrowth in exposed air. The NF3/NH3 remote plasma clean results, on the other hand, are lower and more consistent because the preclean chamber is in situ to the PVD Ni chamber on the same high vacuum mainframe.
Conclusion
Electric test results confirm the effectiveness of using NF3/NH3 remote plasma preclean for CMOS device fabrication employing Ni silicide. The NF3/NH3 remote plasma preclean can achieve low sheet resistance and improve junction leakage. Analyses show that a surface cleaned with a NF3/NH3 remote plasma preclean process is nearly as smooth as that cleaned with HF wet clean, and, like HF wet clean, it can also form a defect-free NiSi layer. However, unlike HF wet clean, NF3/NH3 remote plasma preclean does not have queue-time issues as it is an in situ process with Ni deposition.
We have shown that a NF3/NH3 remote plasma preclean, as opposed to conventional HF wet clean and Ar sputter preclean, may be the most suitable surface preparation before salicide film deposition. It is an enabling technology for NiSi integration for 90nm and beyond SOC CMOS devices.
Acknowledgments
The authors would like to thank Keiichi Tanaka of Applied Materials Japan, and Xinliang Lu, David Or, Jianxin Lei, Gigi Lai, Kishore Lavu, Chong Jiang, and Kevin Moraes of Applied Materials for process work and discussion.
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Takashi Kuratomi received his BSEE from Yokohama National University and his material science and engineering masters from Tokyo U. He is supervisor for Applied Materials Japan, Yokoso Rainbow Tower 8F, 3-20-20, Kaigan, Minato-ku, Tokyo, Japan; ph 81/3-6812-6840, e-mail [email protected].
Daniel L. Diehl received his BSEE from San Diego State U. He is senior manager for Applied Materials Japan.
See-Eng Phan received her BS from Cornell University and her PhD in chemical engineering from Princeton U. She is a member of the technical staff for Applied Materials.
Chien-Teh Kao received his PhD in experimental solid-state physics from the U. of North Carolina. He is technology director for Applied Materials.
Takuya Futase received his material science and engineering masters from the Muroran Institute of Technology. He is process manufacturing engineer for Renesas Technology Corp.
Kazuyoshi Maekawa received his metallurgy and materials science masters degree from Kyoto U. He is R&D senior engineer for Renesas Technology Corp.