Issue



Driving yield learning with advanced scan-based fault isolation


01/01/2007







As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating causes of failures. Meanwhile, analysis costs are increasing due to the amount of time needed to locate the physical defect. One solution to the yield-analysis problem is scan diagnosis-based fault isolation. Previous scan diagnosis-based techniques neither provided enough information about the type of fault nor inspired enough confidence in the diagnosis. With new scan diagnosis algorithms, it is now possible to not only isolate a fault, but also to identify the type of fault as well as assign each “suspect” a confidence ranking prior to destructive analysis.

Yield analysis of submicron devices is an ever-increasing challenge. The difficulty is compounded by the lack of in-line inspection data as many companies adopt foundry or fabless models for acquiring wafers. In this scenario, failure analysis is increasingly critical to help drive yields. Failure analysis is a process of fault isolation, or a method of isolating failures as precisely as possible followed by identification of a physical defect.

Scan-based diagnosis is routinely used for fault isolation on individual failures [1-11]. Recently, it has also been shown applicable to yield improvement [1, 2, 12-15]. The diagnosis tool employed for this study is suited for analysis of one-of-a-kind failures as well as failures from manufacturing that can be used for yield learning.

Yield learning

Yield learning requires a high-performance diagnostic tool to process statistically sufficient failure data. Besides performance, the key features of a scan diagnostic tool necessary to drive yield-learning efforts are defect classification and suspect ranking. The tool employed for this study utilizes a location-based approach to identify the suspects. It also classifies the suspects and assigns a score for each one, indicating how well its behavior matches with the observed failures on the tester. The general flow of this approach is described as follows:

First, for each failing pattern, the diagnosis tool simulates each single gate pin location with failure (the location has opposite logic value from good machine value) to see whether the failing pattern can propagate the failure to all observable points with the same behavior as observed on the automatic test equipment (ATE). Second, if the scan diagnosis tool finds any correlation, the failing pattern is explained by that location. Third, a heuristic method finds a set of minimal faults that can explain all the failing patterns. The heuristic method can be a minimum set covering algorithms [1, 2] or a probability-based method [7].

Furthermore, the diagnostic tool separates all fail data into several independent symptoms. For each symptom, the tool lists the suspects that explain the failing patterns in that symptom. New diagnostic algorithms are added to classify suspect behavior, and a formula is used to give a score for each suspect such that, for each symptom, all suspects are ranked.

Classifying suspect behavior

The tool used in this study classified all suspects into the following categories:

  • STUCK: A stuck-at 0 or stuck-at 1.
  • OPEN/DOM: This category is used for suspect nodes that fail both a 0 and 1 state during different patterns. This suspect could be caused by an open along a single route or a dominant bridge between two or more routes.
  • BRIDGE_2WAY: A 2-way bridge that acts as a wired-OR / wired-AND logic failure. A logic-high / logic-low on either signal causes both signals to pull to a high / low value.
  • BRIDGE_3WAY: A bridge affecting three lines.
  • EQ#: The suspect is equivalent to another suspect listed above.
  • INDETERMINATE: The suspect always fails as a low or a high state, but does not cause some patterns that failed on the tester to fail in simulation and therefore cannot be classified as stuck-at.

Ranking suspects

Besides classifying suspect behavior, the new algorithm scores each suspect based on a formula that calculates the similarity of simulated behavior vs. what was observed on the ATE. Different suspect types can have different simulated behavior even if they are at the same logical location. For example, a bridge suspect should have fewer failing patterns than a stuck-at suspect at the same location. The score is normalized from 1 to 100; a higher score reflects a good match between simulated fault and observed ATE failure. All suspects of each symptom are ranked. The tool has an option to list the percentage of suspects of each symptom. By default, the scan diagnostic tool lists the suspects with scores higher than 80 or ranked top three of each symptom.

Diagnosis output

Figure 1a shows a sample scan diagnosis output. It begins with a tracking information section for failing die, which if included in the failure file would appear unchanged in the diagnosis report between the keywords tracking_info_begin and tracking_info_end. Next is the global information section about diagnosis such as total number of symptoms, total number of suspects, CPU time spent on diagnosis, input failure file information, and finally number of failing patterns, number of passing patterns, and number of unexplained failing patterns. Information about each symptom is then listed.


Figure 1. Scan diagnosis outputs: a) using a test chip and b) using an advanced scan diagnosis.
Click here to enlarge image

For each symptom, the following data is provided: ID, number of suspects for that symptom, the number of failing patterns explained by that symptom, and failing pattern numbers. Following this is the list of suspects for that symptom. Provided for each suspect are ID, score, fail-match (the number of failing patterns for which simulated and tester observed behavior match), pass-mismatch (the number of passing patterns for which simulated and tester behavior does not match), type, value, and location composed of pin path name, cell name, and net path name.

All suspects within a symptom explain the failing patterns listed for that symptom and their score reflects how well they explain the passing patterns as well as the failing patterns. During score computation, priority is given to explanation of failing patterns and a penalty is applied if a suspect causes mismatches for passing patterns. A suspect with a score of 100 perfectly explains all the failing patterns and passing patterns. In general, the higher the score, the better. In cases where a failing device has multiple defects, the diagnosis report contains multiple symptoms.

The experiment and case study

A test chip was selected for use during ongoing yield analysis. This test chip was built on a CMOS 0.11µm low-k technology with six layers of metal routing. Failures were logged for scan diagnostics. The number of failures to data log is crucial. If too few failures are collected, diagnosis may not be as accurate, but if too many failures are collected, the amount of test time and therefore test cost can increase drastically. For the purposes of this experiment, 200 failing cycles were collected for each failing device.

Scan diagnostics were performed on 12 failing devices. The advanced scan diagnosis algorithm was able to identify possible fault locations on 10 of the 12 devices. Seven devices were diagnosed with suspects having a rank of 100; the remaining three devices all contained suspects of rankings between 70 and 90. One of the ten analyzed devices is detailed below.

Advanced scan diagnosis identified one symptom with two possible suspect candidates (Fig. 1b). Suspect 1 was identified as a STUCK-0 on the Z output of a NAND gate. Suspect 2 was identified as a STUCK-0 on the A input of an XNOR gate. The advanced scan diagnosis algorithm lists the second suspect type as EQ1, indicating the second suspect location was equivalent to suspect location one.


Figure 2. Fault candidate schematic.
Click here to enlarge image

Figure 2 shows the schematic of the identified fault candidates. Notice the Z output of the NAND gate drives the A input of the XNOR gate with no additional fanouts. For this reason, the algorithm identifies both locations, indicating the physical defect may be located internal to the NAND, XNOR, or on the metal routing between them. With the fault isolated, the remaining analysis can now focus on the two suspect logic gates prior to any destructive analysis. Physical layout analysis of the identified node between the two logic gates revealed the node of interest is routed at the Metal 3 layer and below.


Figure 3. I/V curve of the node identified by scan diagnosis.
Click here to enlarge image

The die was deprocessed using a combination of chemical etch and parallel lapping to expose the metal three node of interest. The suspected node was electrically evaluated using SEM in-chamber nanoprobes. At the Metal 3 layer, the Z output of the NAND gate was intact. Electrical analysis of this node should exhibit both an n-p and a p-n diode. Figure 3 shows the IV curve of an n-p junction diode observed on the suspected node.


Figure 4. FIB cross-section of open p active contact leading to a stuck-at 0 scan failure (Suspect ID 2).
Click here to enlarge image

Additional physical layout analysis of the driving NAND gate revealed single contacts to both n and p active outputs. It was determined that an open p active contact would cause a stuck-at-zero signature and yield only an n-p diode. Focused ion beam (FIB) cross-section analysis of the suspected p active contact confirmed the p active contact to be unlanded due to a blocked etch, as illustrated in Fig. 4. It is important to note that the defect was an open, but due to its location in the circuit, it behaved as a stuck-at defect.

Conclusion

Yield analysis is a crucial part of the fabrication process. Providing accurate and timely data to a fab is invaluable when attempting to increase wafer yields. Through the use of advanced scan diagnostics, root cause analysis can be performed in a short amount of time with high-root cause success rates. A method has been described that incorporates updated fault modeling that allows for diagnosis of open and bridging as well as stuck-at faults.

This new technique also provides information about the suspected fault type and then ranks each suspect according to how well it describes the observed failure. Once the fault type is determined and suspects identified, the physical failure analysis can be biased towards the specific fault/suspect, decreasing the amount of time spent in the de-process/analyze loop.

With all suspects ranked, electrical analysis can focus on the most probable defect location, decreasing the root cause cycle time. Physical layout analysis still plays an important role in determining how far to deprocess a device and what electrical characteristics should be observed at each layer. Although advanced scan diagnosis can isolate the suspect precisely, the time spent analyzing each defect also depends on the metal stack and complexity of suspected nodes. With high-root cause success rates and short cycle times, advanced scan-based fault isolation can be used to drive yields.

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Chris Eddleman is an internal failure analysis engineer at LSI Logic, 2001 Danfield Court, Fort Collins, CO 80525; e-mail [email protected].

Wu-Tung Cheng is a chief scientist in the Advanced Design for Test Products division at Mentor Graphics Corp.; e-mail [email protected].