Technology News
12/01/2004
Selete says batch CVD HfSiOx film best choice for high-k gate dielectric
Work at Selete (Japan’s semiconductor technology consortium) finds high-k gate dielectric film made of HfSiOx reduces gate leakage just as well as HfAlOx, and it can be made much more efficiently with a batch CVD process instead of atomic layer deposition (ALD). Carrier mobility, threshold voltage, and off-current leakage were also essentially the same for both materials, suggesting that ease of manufacturing, not performance, can be the deciding factor for high-k gate dielectrics.
Though industry consensus has settled on some sort of hafnium compound as the best material for improving the insulating properties of ever thinner gate films, it’s less clear which heat-resistant material to best add to the hafnium to prevent it from crystallizing at low temperature. One common approach to maintaining the hafnium in an amorphous state through the heat of processing is to add SiO2 to the HfO2 (hereafter referred to as HfSiOx). A newer approach is to add Al2O3, which has a higher k value (hereafter HfAlOx), though little data on its performance has been reported.
We made our HfSiOx with a batch CVD process. We first made a SiO2 base layer, then deposited the HfSiOx, followed by ozone oxidation and ammonia nitridization. Hf density was about 60%.
We made our HfAlOx by ALD. First we made a SiON base film by rapid thermal oxidation, then deposited a HfAlOx layer with ALD, then did a post-deposition anneal in a rapid thermal processing tool. Hf density was about 30%.
Though higher-purity versions of both materials performed better, there was essentially no difference in current leakage between the two materials (see figure).
 Different materials result in almost no difference in gate leakage. (Source: Selete) |
Carrier mobility was also very similar. Adding nitrogen in a SiON base layer prevents cross-contamination with the HfAlOx and improves its mobility, while adding nitrogen to the HfSiOx for better heat resistance reduces its mobility, so the end result is about the same. Electron mobility curves for both peak around 200-250cm2 V-1 s-1 at an electrical field of 0.4 MV/cm and beyond. Threshold voltage is slightly better for HfAlOx.
The off-current leakage for both materials is much the same, with both easily meeting the criteria needed for 65nm low standby-power devices.
Since performance is the same, we think HfSiOx is the better alternative and will be the mainstream high-k choice, because it can be made with an efficient batch CVD process, and, if it is processed at a low enough temperature, does not need nitridization.
- T. Arikado, H. Kitajima, and K. Torii, Selete, from SST partner Nikkei Microdevices
Fewer steps, more flexibility for lead-free wafer bumps
Aiming at the evolving requirements for lead-free semiconductor packages, IBM Corp. and Süss MicroTec AG are collaborating to commercialize a relatively simple technique for depositing solder balls and metal contacts across large-diameter wafers using IBM’s next-generation wafer bump technology called C4NP.
According to the two companies, the C4NP (controlled-collapse chip connection new process) is the first flip-chip technology to support 100% lead-free packaging needs with a combination of fine-pitch connections, low cost, and the flexibility to use “virtually all types of solder compositions.”
“The industry has not settled on the right metallurgical composition for lead-free packaging,” notes Joe Lisowski, IBM director of worldwide applications and packaging development. “There are still a lot of different competing technologies, in terms of solder compositions. The C4NP process allows for the ultimate flexibility, from a metallurgical standpoint.”
 Device wafers and solder-filled mold plates join up for transfer of contacts after inspection. |
For several years, IBM’s T.J. Watson Research Center has been working on C4NP concepts based on injection-molded soldering (IMS), which lowers wafer bumping costs by reducing process steps compared to traditional photo stencil/screening, electroplating, and evaporative techniques. The IMS process melts bulk solder - lead or lead-free (ternary and quaternary) alloys - and dispenses the solder into a wafer-sized mold, which has the same coefficient of thermal expansion (CTE) as the silicon devices being bumped. In the C4NP process being commercialized by the IBM/Süss alliance, reusable mold plates are made with glass (see figure). These molds can be cleaned and reused ~100 times, based on current tests.
The glass molds are scanned with molten solder, filled, and cooled to solidify the solder. The mold plates are then aligned with wafers to place the patterned solder bumps and balls on the contacts of devices. After a reflow step, the mold is removed from the wafer, leaving solder bumps.
Under the alliance, IBM’s Systems & Technology Group will continue research and optimization of C4NP techniques while Munich-based Süss MicroTec will develop a complete line of 200mm and 300mm wafer tools for commercialization of the technology. IBM will also provide on-site process training to customers purchasing commercial systems from Süss. A license for C4NP technology will be included with the purchase of Süss equipment, which is scheduled to become available in 2H05. IBM is finishing C4NP development for internal use.
“Süss believes this has the potential to become an industry standard. Essentially, it is a disruptive technology,” says James Quinn, executive VP at Süss MicroTec. “Until now there have been limited options for applying lead-free solder with existing flip-chip technologies,” he adds, citing industry efforts to remove lead from IC packages to meet environmental guidelines.
Traditional screening or photo stencil techniques are relatively simple, but these approaches face limitations in handling fine-pitch contacts and large wafer sizes, according to IBM and Süss. Electroplating can produce fine-pitch contacts, but there are limits to lead-free alloys. Evaporative processes also fall short in making fine-pitch contacts, and costs become an issue with the introduction of new lead-free solder compositions, say IBM and Süss.
“The C4NP process is simple, from a manufacturing standpoint. You can queue up the glass molds and have them wait for wafers,” explains IBM’s Lisowski. “There is rapid turnaround from the time molds are joined with wafers. The reflow time is short. The molds are cleaned and then ready to go again.
“We also get rid of a lot of plating chemistries that have to be managed as waste,” he adds.
IBM and Süss say the C4NP process easily accommodates binary, ternary, and quaternary alloys and minimizes the cost of consumables because only solder balls are created and transferred to the wafer without waste. The C4NP supports solder bumping of 200mm and 300mm wafers with similar efficiency, according to the two companies, which say the process has demonstrated technical capabilities exceeding requirements in the current ITRS. IBM says it has produced C4NP solder bumps with 150µm pitch in its pilot line. Lab results have proven 50µm pitch is feasible.- J.R.L.