Integrated dielectric trench-depth measurement for dual damascene
12/01/2004
Device fabrication at the sub-90nm technology node mandates that integrated metrology equipment measure complex structures and new materials directly on virtually every patterned production wafer, without sacrificing throughput. Addressing this and other challenges, such as the need for on-die (device) measurements, can add to an IC manufacturer’s costs. This article describes the effectiveness of large spot-size Fourier transform spectral reflectometry in tackling these issues for dual-damascene copper interconnect processing at the 90 and 65nm nodes.
Advanced equipment control/advanced process control (AEC/APC) is becoming critical to maintaining consistent process performance as wafer size increases and device geometry aggressively shrinks below 90nm. Leading IC manufacturers [1-3] have implemented AEC and APC capabilities into their production lines, resulting in higher yields and reduced cycle times. The requirements, however, present tremendous challenges to traditional process-control methods, which create a need for integrated metrology modules (IMM) on process tools.
APC in a 300mm fab must be fast enough to ensure a second wafer can be processed with information generated from a first wafer, and must do it reliably from wafer to wafer, with no impact on throughput. The objective [4, 5] is to feed wafer information forward to the next processing step or backward to the process equipment for fine-tuning prior to processing subsequent wafers. This is the function of IMMs.
Many integrated thickness-measurement modules are based on technologies developed for standalone tools and are sized to accommodate a smaller package. Repackaging typically retains the optical design and accessories for pattern recognition, causing both technical and economic disadvantages [6-8]. For example, metrology tools using a small optical spot typically require large, unpatterned “test” areas and often fail at pattern recognition when the process deviates beyond certain limitations, thus reducing throughput and risking false measurements in a production environment.
For trench etch APC, optical critical-dimension (OCD) metrology is employed to determine trench width (CD) and sidewall profiles, in addition to trench depth. This technology is expensive, however, and requires a special, large-area test structure, adding more “real estate” cost to a wafer. Versatility may be further reduced because OCD metrology cannot measure thicknesses over multiple metal levels where trench depth is a critical parameter, more so than CD or sidewall profile. In general, the trench depth is more sensitive to process changes than CD and sidewall profile.
Beyond the 90nm technology node, another metrology issue arises: Measurements typically taken on large unpatterned areas and test structures often do not accurately represent the fabrication process results on die structure. Information about the effect of a process on different structures is a prerequisite to process and device-performance optimization, which can only be achieved with measurements taken directly on patterned structures within the die. One solution is to use large spot-size Fourier transform spectral reflectometry.
Measurement system and technology
A Tevet IsTMS film-thickness measurement system was used for this work. The system is based on large spot-size Fourier transform broadband spectral reflectometry; unlike classical reflectometry, which uses a small spot aligned to designated test sites or large unpatterned areas, this method uses a light beam that is comparable in size to a die and does not require specified test regions.
During measurement, a single broadband light source is distributed to five optical heads through optical fibers. Each parallel beam optic emits a 20mm dia. light beam onto the wafer. Detectors collect normally reflected light, which is sent through a second optical fiber to a spectrometer where the light is dispersed. The resulting digitized spectra are then transferred to the system’s computer, where proprietary algorithms deconvolve the signal into individual thicknesses [6-8].
The reflectance spectrum from each optical head contains periodic oscillating functions, sin(2π × n × D × 1/λ), where n is the refractive index and D is the film thickness. The periods of the functions, Δ(1/λ), are determined from the thicknesses of all the films under the 20mm light spot and can be expressed as n × Di × Δ(1/λ) = 1, where Di is thickness of the ith film. The reflectance spectrum, R(λ), can then be converted to a thickness spectrum, R(D) by applying spectral analysis techniques such as Fourier transformation (FT).
Unlike classical reflectometry where knowledge of the optical characteristics (refractive index, n; extinction coefficient, k; and thickness, D) of the film and film stacks of interest is required, the IsTMS can transform standard reflectance data into Fourier space, decoupling thicknesses from one another and generating an independent peak for each thickness. By fitting the FT curve with provided refractive indices, thickness values are determined. The thicknesses corresponding to each device structure can be identified with the addition of device structure information [6-8].
Experimental results
The presence of trenches in dual-damascene processes poses considerable challenges to thickness and OCD metrology. For example, trench density and width can create process loading effects, which can lead to thickness variations, depending on the device structure. Measurements taken on test structures do not accurately reflect the resulting layer thickness on a die. Furthermore, trench depth can be more sensitive to process deviation than trench CD. Controlling etch depth is difficult because dielectric film stacks do not contain an etch stop layer. Over-etch produces electrical shorts; under-etch produces breaks in metal lines.
 Figure 1. Dual-damascene interconnect layers are shown, with trench widths as small as a) ~90nm for Wafer 1 and b) ~65nm for Wafer 2. |
In this study, the IsTMS system, configured for 300mm-wafer process control, was used to measure two patterned dual-damascene interconnect wafers, post-oxide etch and resist/antireflective coating (ARC) strip. The two wafers represent different processing technologies and integrations. The results were compared with SEM data.
Schematics of the trench structures and film stacks of Wafer 1 and Wafer 2 are shown in Fig. 1. Wafer 1 is a full 300mm wafer, patterned with trenches nominally ranging from 90nm to tens of microns wide, with a ~3:1 aspect ratio, and containing an uncapped low-k film with k ~3.7. Wafer 2 is a piece of 300mm wafer patterned with trenches nominally 65nm to tens of microns wide, with a ~4:1 aspect ratio, and containing a capped low-k film with k ~2.8. The wafers were etched with different chamber hardware and process recipes.
Thickness measurements
Thickness measurements are used to determine trench depth, penetration thickness into the oxide film, and the low-k film thickness prior to etching. Generally, the five optical heads are preconfigured to meet specific test requirements. For this study, the sensors are placed over measurement sites on Wafer 1 (Fig. 2a) at the wafer center (1), and 100mm (4", 5") and 124mm (2, 3) from the center. The five sites are simultaneously measured and the wafer was rotated 90° to obtain measurements at locations 2", 3", 4, and 5. Four measurements were taken at wafer center and two measurements at each of the other measurement sites.
 Figure 2. Measurement sites as they appear on a) Wafer 1 and b) Wafer 2, where open circles represent the optical beam spot. |
Thicknesses of oxide layers were measured using the FT spectral analysis option. D1 is the film-stack thickness adjacent to the trenches (nonetched) and D2 below the trenches (etched). D3 is the total thickness of the top two layers and D4 is the oxide-cap thickness in Wafer 2. Trench depth represented by Δ1, penetration thickness into Oxide 1 by Δ2, and low-k thickness by T were calculated with measured D1, D2, D3, and D4. The films represented by D1 to D4 in Fig. 1a and 1b are summarized as follows: D1 = unetched, D2 = etched, D3 = oxide cap + low k, and D4 = oxide cap.
Trench depth is determined by subtracting the measured film thickness below the trenches from the measured total thickness of the film stacks adjacent to the trenches:
Δ1 = D1 − D2 (1)
For Wafer 1, the refractive index of the CVD oxide film was used to calculate all thicknesses. The refractive index of the low-k film is comparable to that of the CVD film; therefore, the thicknesses of these two films cannot be separated. The calculations of D1 and D2 include the equivalent oxide thickness (EOT) of the unknown layer, which was canceled out during the subtraction for Δ1. The EOT Dox is defined as physical thickness D times a ratio of its refractive index n to oxide refractive index nox (e.g., nox × Dox = n × D).
For Wafer 2, the refractive index of the low-k film is different from the other oxide films and therefore is included in the thickness of D1 and D2. Because of the difference in refractive index, the interfaces between the low-k film and the oxide films above and below the low-k film are optically observable; therefore, D3 and D4 are measurable. Consequently, two important parameters, penetration thickness, Δ2, and the low-k film thickness, T, were obtained:
Δ2 = Δ1 − D3 = D1 − D2 − D3 (2)
T = D3 − D4 (3)
Die locations and measurement sites on Wafer 2 are shown in Fig. 2b. The half-moon wafer piece was positioned so that only one optical head was used to measure various sites on the wafer. Die grids are represented by gray rectangles and measurement sites are marked with large open circles, representing the beam spot size. Four sites within a die in the top row dies were measured because of the different densities of trenches at these sites.
Results and discussion
A nine-point wafer map was obtained, showing trench depths at various measurement sites on Wafer 1 (Fig. 3). The data indicate a disparity in trench depths between the upper and lower halves of the wafer, and variations in depths at the center of the wafer of 3.4% from the edge.
To verify the trends indicated by the results, comparisons were made to SEM cross-sections on comparable sites. Figure 3 plots SEM results obtained at the wafer’s center and edge on the same scale as the reflectometry measurement. SEM results show depths of the wider trenches at the wafer center are comparable to those at the wafer’s edge. However, depths of narrower trenches at the wafer center are smaller than those at the wafer’s edge. This implies that SEM results are trench-width dependent. Additionally, the same increase in trench depth is indicated with comparable absolute numbers and within-wafer uniformity for the narrow trenches. The narrow trenches represent a majority of the trenches in a die and therefore contribute more intensity to the reflectance spectra than wide trenches.
Since trench depth is related to etch rate, these results could be used to substantiate etch performance. The difference in trench depth between the two halves of the wafer was consistent with the etch rate difference between the halves observed by an end user.
Advanced etching processes were used on Wafer 2, wherein the trenches were narrower and the dielectric k value lower than for Wafer 1. Figure 4 displays the IsTMS trench depth (Δ1) results (left axis), calculated from Eqn. 1 as a function of R, the distance between a measurement site and the wafer center. A slight decrease in trench depth with increasing R was measured. Trench-depth uniformity (3σ) was determined to be <3.2% across the wafer piece.
 Figure 4. On Wafer 2, trench depth, Δ1, closely tracks penetration thickness in oxide film, Δ2. |
Accurately etching a trench to a given depth is critical to device performance and yield. Equation 2 was used to calculate penetration depth, Δ2, as a function of R on Wafer 2. The influence of the etch depth on penetration thickness is illustrated in Fig. 4 (right axis). The Δ2 profile closely tracks the Δ1 profile.
Results of the low-k film thickness, T, calculated from Eqn. 3 prior to the etch process are shown in Fig. 5. The uniformity of the low-k film was such that it resulted in the tight profile tracking between Δ1 and Δ2, shown in Fig. 4.
 Figure 5. Thickness uniformity on a low-k film on Wafer 2. |
The thickness measurement of the low-k film after etch implies the possibility of measuring the low-k film thickness before etch. Prior to etch, the low-k film/oxide cap was partially covered by photoresist. After etch, the uncovered low-k film/oxide cap was removed, leaving the covered portion unetched, with no photoresist coverage during the reflectometry measurement. Regardless of changes in film stack and film structures, location of the low-k film thickness peak in the FT spectra R(D) is independent of the presence of other films, and therefore can be obtained before, as well as after, the etch.
SEM cross-sections were obtained from Wafer 2 for narrow trenches only. [Ratios of ISTMS/SEM values are: trench depth (Δ1) = 1.009; penetration Δ2 = 0.853; low-k film thickness (T) = 0.961.] (Average thicknesses were normalized to the average SEM thickness. Measured trench depth matched the SEM results to within 1%. Penetration depth, typically on the order of a few hundred angstroms, deviated by 15% due to the low SEM resolution of 50-70Å. This is an order-of-magnitude coarser than the angstrom resolution using the large-spot reflectometry method. Given the thickness of the low-k film, >1000Å, there was only a 4% discrepancy between the two measurements.
Conclusion
IMM based on large spot-size spectral reflectometry is a nonintrusive, nondestructive method for measuring the thickness of small trench features on device areas, anywhere on the wafer, including sites within a die, independent of high pattern density. The method demonstrated the capability to determine three important thicknesses for dual-damascene processes: trench depth, penetration depth due to over-etch, and low-k dielectric thickness. SEM cross-sections were used to verify accuracy. Process information was achieved on device structures and the wafer map generated provided uniformity data. With speed and resolution that exceeds other nonintrusive metrologies, IsTMS meets the requirements of APC and sub-90nm design rules.
Acknowledgment
The author appreciates support provided by Tevet.
References
- M. Liu, keynote speaker, “APC from a Foundry Perspective,” AEC/APC Symposium XV, Sept. 2003.
- J. Pettinato, et al., “An ITRS View on Future Process Control Challenges and Opportunities,” AEC/APC Symposium XV, Sept. 2003.
- T. Sonderman, et al., “Advance Process Control Technology Evolution Requirements for 300mm Manufacturing,” AEC/APC Symposium XV, Sept. 2003.
- K. Faron, et al., “Deployment of MIMO Process Control in the Semiconductor Industry,” Plasma Etch User’s Group Meeting, April 2004.
- A. Skumanich, et al., “Advanced Etch Applications Using Tool-Level Data,” Plasma Etch User’s Group Meeting, April 2004.
- Technical presentation, Semicon West 2004.
- A. Dag, et al., “Performing STI Process Control Using Large-Spot-SizeFourier-Transform Reflectometry,” Micro, p. 25, April 2003.
- Tevet’s demo/interim progress reports.
Ying Wang received her BS in physics from Beijing U. and PhD in physics from the U. of Kentucky and is senior applications technologist at Tevet Process Control Technologies, 5673 W. Las Positas Blvd., Suite 213, Pleasanton, CA 94588, ph 925/734-6701, e-mail [email protected].