NEC cuts 65nm standby power by two orders of magnitude
11/01/2004
NEC has cut standby current leakage at the 65nm node by 30–100× by using HfSiON as the high-k gate dielectric and a transistor structure optimized for Transmeta Corp.'s LongRun2 technology to dynamically adjust the body bias as well as the supply voltage.
The company plans to use this same low-power technology in products across all applications, from portable phones emphasizing reduced power usage, to high-end servers focusing on fast performance. The approach reduces standby leakage current roughly from the range of 10-7A to that of 10-9A in high performance devices, or from around 10-10A to around 10-12A in low-power applications.
While the high-k dielectric cuts the gate leakage, NEC gets more power reduction from using Transmeta's LongRun2 package of circuits and algorithms to monitor the chip's activity and adjust both the supply voltage and the body bias as needed (Fig. 1). Cutting the supply voltage when not needed for performance reduces power usage, and limits gate-induced drain leakage and gate leakage. However, the lower supply voltage requires lower threshold voltage to maintain transistor performance, and lower threshold voltage means more subthreshold leakage. Thus, the system adjusts the body bias to significantly reduce this subthreshold leakage as well.
NEC structures the transistor so changing the body bias produces a big change in threshold voltage, without the usual reliability problems, or the increase in gate-induced drain leakage. The same design can be used from high-speed to low-power modes.
 Figure 2. Optimized transistor structure. (Source: NEC Electronics) |
Usually shorter gates create a short channel effect that reduces threshold voltage, and changes in body bias produce only small changes in threshold voltage. And adjusting the body bias increases gate-induced drain leakage. But we controlled these problems with an optimized source-drain structure, and a well with sides steeply sloping in toward the top (Fig. 2). This shape concentrates impurities toward the bottom of the channel, away from the surface where they would increase the threshold voltage, while allowing the high density of impurities needed to enable large changes in threshold voltage with changes in body bias. With this optimized structure, off-leakage can be reduced by two orders of magnitude by adjusting the body bias to as low as 10-9A/µm with supply voltage of –2V.
We set three operating modes for the device. The high-speed mode uses a 1.2V supply voltage and 0V body bias, for standby current of <200nA/µm. The power-saving mode uses a 0.6V supply voltage and -1V substrate bias for <2nA/µm standby current. Normal mode is in between, with <20nA/µm standby current. Active power requirements in normal mode are about 50% that of high-speed mode; those in power-saving mode are about 10%. Standby power requirements are reduced to about 13% of peak in normal operating mode, 7% of peak in power-saving mode.
While adjusting the body bias significantly reduces off-leakage, it can cause problems with device reliability. We found no effects on time-dependent dielectric breakdown or hot carrier injection, but adjusting body bias did increase the negative bias temperature instability. But by reducing the supply voltage to a level in the acceptable range for each body bias setting, the impact on device life can be reduced to where it is no longer a problem. Values for our three modes are all within these ranges.
We use HfSiON for the high-k gate dielectric because it remains amorphous at the 1050°C CMOS process temperatures instead of crystallizing, and its low defect density means low hysteresis. Gate leakage with the HfSiON dielectric is 2.5 to 3 orders of magnitude smaller than with a SiON layer with an SiO2 equivalent oxide thickness of 1.6nm.
Because the HfSiON gate dielectric reduces both gate leakage and gate-induced drain leakage, and can be thinner than SiO2, it gets the highest on-current with the lowest standby current yet reported for a polysilicon/high-k transistor — on-current of 520µA/µm and standby current of 17pA/µm, with a supply voltage of 1.2V.
HfSiON's problem with Fermi-level pinning is actually an advantage: It increases the threshold voltage, which reduces the off-current.
To prevent the implanted P ions from dispersing from the polysilicon into the HfSiON to cause long-term reliability problems, we put a layer of amorphous silicon in between. This barrier layer keeps the P out of the HfSiON and cuts the lifespan reduction from nMOS positive bias temperature instability by two orders of magnitude.
Yasushi Yamagata and Kiyotaka Imai, NEC Electronics Corp., Advanced Device Development Div., SST partner Nikkei Microdevices