Parallel test techniques reduce test costs

11/01/2004

The 1999 SIA roadmap predicted a transistor's cost-of-test (COT) would exceed its fabrication cost by 2012. COT reduction strategies include testing less, more efficiently, and differently, as well as reducing the cost of the testers used [1]. Applying a typical cost-of-ownership model to parametric test in volume production, then performing sensitivity analysis, reveals that while cutting initial capital equipment cost by 50% decreases COT/wafer by 15%, a 50% test time reduction delivers a COT/wafer decrease of nearly 50%. Testing more efficiently is clearly the more effective strategy for reducing parametric COT.

Parallel parametric testing

Today's parametric testers can have up to eight source-measure units (SMU). When measuring a resistor sequentially (requiring one SMU), up to seven SMUs are idle. By simultaneously measuring multiple device types within a single probe touchdown and increasing hardware utilization, parallel test increases throughput significantly. For example, two resistors, one diode, and one transistor could be measured simultaneously by asynchronously performing different connect-force-measure sequences on all four devices at once. Details on parallel test implementation and test structures are available elsewhere [2].

Parametric parallel test offers different benefits depending on when it is being used in a given process node's life cycle. It can acquire more data in the same test time during process development, or the same amount of data in less time during volume fabrication.

Volume production

One logic IC manufacturer performs 300 parametric tests/site on a variety of devices. Fast integration (17 msec) for signal averaging is used, and the fab's philosophy is to optimize test structures for data integrity. Test devices share few probe-contact pads and the scribe line test insert isn't optimized for minimum area, allowing significant parallelism with existing test structures and probe cards. Parallel testing let this fab achieve 1.7× higher throughput in measurements at the sites overall, excluding wafer movement time between sites. Test time was reduced by 42%, from 98 sec in sequential test mode to 56 sec in parallel.

Process development

Acquiring more data in the same amount of time is invaluable during process development, when the learning curve is steepest and the opportunity to shorten time-to-market is greatest.

Voltage-ramped breakdown (VRB) is a reliability test for characterizing gate capacitors and interlevel dielectrics (ILD). For the copper damascene process, it's an important indicator of copper diffusion barrier layer and capping layer interface integrity. The typical test structure for ILD reliability in a copper/low-k process is an interdigitated metal-dielectric comb structure. In this destructive test, voltage across the dielectric is ramped from 0V to as high as 100V, while leakage current is monitored. An abrupt leakage current increase indicates the dielectric has catastrophically broken down; the voltage bias immediately before breakdown is recorded.

The statistical nature of the failure mechanisms requires measuring many dice across the wafer, with cumulative probability of breakdown voltages compared between different processes. Test time depends more on the voltage at which the dielectric fails (good devices take longer to test) and less on whether multiple devices under test (DUT) are measured in parallel.

A typical ramp rate for the VRB test of comb capacitors with low-k dielectric might be 1V/sec, which is slow relative to other breakdown tests because the voltages can be quite high and leakage currents transient for low-k dielectrics. If breakdown occurs at 5MV/cm with a 0.2µm dielectric spacing, it would take 100 sec to reach the 100V breakdown voltage. Faster ramp rates would produce even higher breakdown voltages (potentially exceeding the tester's voltage limit or changing the comb structure's failure mechanism) because the effective time at a voltage is less.

This test's length requires limiting the number of dice tested to obtain reasonable throughput. A standard wafer-sampling strategy might be to measure 16 of the 121 dice available, and only one of the 12 structures within a die. Process effects such as dielectric erosion and other phenomena always occurred on spatial scales consistent with the chosen die sampling that spanned the wafer, so measuring more structures in closer proximity (more than one device/die) wasn't thought to provide additional process information.

Cumulative probability plot of VRB test results.Click here to enlarge image

The test time for 16 dice was ~1 hr. Measuring four DUTs in parallel within the same die wouldn't increase the test time, so three more DUTs were measured in parallel at each site in the interest of discovering new processing phenomena. The figure is the resulting cumulative probability plot of VRB test results.

When testing only one device/die, the median breakdown field was ~4MV/cm with a very broad Gaussian distribution and no sign of multimode failures. One might conclude the dielectric layer's integrity was compromised across the wafer, so it and the process it represents should be rejected. The curve for the four DUTs combined, acquired in nominally the same test time, showed the median breakdown field was 50% higher at 6MV/cm and the distribution appeared bimodal, indicating there might be a localized process issue affecting the dielectric, but its general integrity was good. This conclusion differs significantly from the one drawn from the one DUT/die curve. Failure analysis showed localized cracking of the dielectric passivation layer near the die during test, sufficient to locally degrade the dielectric's breakdown properties.

Opportunities going forward

Parallel parametric test delivers the same data in substantially less time in volume production and substantially more data (and learning) in the same time during process development. When test structure development for parallel test is coordinated with scheduled mask changes, there are ongoing opportunities for decreasing parametric COT in volume production.

References

1. S. Carlson, "ATE Struggles to Keep Pace with VLSI," EE Times, Dec. 13, 2001, http://www.eetimes.com/story/OEG20011213S0026.
2. J. Kuo, S. Weinzierl, G. Alers, G. Harm, "Reducing Parametric Test Costs with Faster, Smarter Parallel Test Techniques," http://www.keithley.com/servlet/Data?id=15590.

Jeff Kuo is a senior applications engineer at Keithley Instruments; e-mail [email protected]. Steven Weinzierl is a product marketer in the business development group at Keithley Instruments. Glenn Alers is senior process manager in the integration group at Novellus Systems. Gregory Harm is a test engineer at Novellus Systems.