No cooling-off period for annealing
11/01/2004
Solid State Technology asked industry experts to predict the future of thermal processing.
Industry must choose anneal approach: revolutionary vs. evolutionary
 Lucia M. Feng |
Lucia M. Feng, director, laser product technology, Ultratech Inc., San Jose, California
A challenge in continued device scaling is the ultrashallow junction (USJ) formation in the source/drain extension areas of advanced transistors. To activate the dopant and repair implant damage, a high-temperature anneal is typically required. Concurrently, anneal technology must have an extremely small thermal budget to minimize the transient-enhanced (TED) diffusion through the silicon device during the dopant activation process, which preserves the abruptness of the junctions for effective control of short-channel effects.
RTP, however, will not be able to achieve the desired junction characteristics for the 65nm technology node and beyond due to inherent limitations. In the current generation of RTP systems, junction anneal subjects the entire wafer to a temperature between 1000°C and 1100°C for a few seconds. This temperature range is too low to achieve desired dopant activation because of solid solubility limits. In addition, significant dopant diffusion takes place in this timeframe. The latest RTP tools — in the regime of spike annealing — attain about a 1–2 sec exposure near the peak temperature of 1100°C. However, the extent of dopant activation with the relatively large thermal budget renders spike annealing unable to meet 65nm device requirements. A conservative approach to this dilemma is to go from spike to flash lamp anneal (FLA).
In FLA, the entire wafer is preheated to 300–800°C prior to the use of xenon or arc flash lamps to "flash" a heating pulse for about 1–5 msec. This approach has shown improvements in junction depth and sheet resistance over spike anneal. One important issue in FLA technology is that the ultrashort heating time sometimes causes slip defects and cracks in wafers, and wafer explosions in the worst cases. It also suffers from poor temperature control when the flash occurs. Moreover, pattern-related temperature nonuniformities (the pattern density effect) are appreciable. These inherent limitations most likely limit adoption of this technology for the 65nm node and beyond.
One interim process being pursued is solid-phase epitaxy (SPE). This technology suffers from defects and large leakage currents associated with residual defects, making it unlikely to be adopted.
A millisecond anneal technology in dopant activation that meets the Xj/Rs targets of the 65nm node and beyond is nonmelt laser anneal. Laser spike annealing (LSA) anneals only the section of the device that sees the laser power. The localized region reaches temperatures just slightly below the silicon melting point of 1412°C in a submillisecond timeframe. Ramping at ~1,000,000°C/sec, LSA heats up only a thin layer of silicon on top. This results in low-resistivity, near-diffusionless junctions.
For all millisecond anneals, one concern is pattern density effect. On a bare device wafer, light absorption varies due to thin-film interference at different structured layers that will result in nonuniform temperature distribution across the die. This is true even for the broadband-wavelength heating source used in lamp-based or flash anneal because the field oxide will always act as an antireflection coating, thus enhancing absorption in field-oxide isolation regions. In LSA, a proprietary hardware-based solution is implemented to minimize pattern dependency. Customers' feedback has confirmed that pattern dependency is not an issue for LSA.
Another concern is ease of process integration. The integration puzzle was cleared when two papers presented at the VLSI Symposium in June showed that LSA can be directly applied to the wafers without additional dummy or absorber layers to achieve uniform heating, hence making laser spike annealing easily integrated into conventional MOSFET process flow. Fung et al. of TSMC simply added LSA to its 65nm baseline process of conventional RTP anneal, and reported a 7% drive-current improvement and reduction of >1Å in polysilicon depletion. Shima and coworkers of Hitachi reported source/drain junction annealing by simply replacing RTP in the conventional production flow by LSA. The 50nm gate CMOS devices demonstrated better threshold voltage rolloff and 10% larger drain currents compared to those by RTP.
The future applications of LSA are many and continue to develop to take advantage of instantaneous temperature-spike heating. For example, the laser thermal energy can be delivered only to the desired film to anneal it or to induce a phase transformation. Dielectric film annealing in the back-end-of-the-line is one such possibility. The limited thermal stability of many of the candidate material systems — mobility-enhanced channels and high-k dielectrics, just to name a few — may benefit from LSA where the almost-zero thermal budget could help retain the conventional CMOS process architecture.
The industry is at a crossroads: The time has come to deviate from its evolutionary approach to new technology adoption, and make a bold move to adopt nonmelt laser annealing for the precise thermal budget control that the technology offers for implant anneals. Its value as a technology booster in achieving half- to one technology-node device performance improvement has already been proven and validated.
Contact Lucia Feng at Ultratech Inc., 3050 Zanker Rd., San Jose, CA 95134; ph 408/321-8835, e-mail [email protected].
FEOL forecast: mini- and micro-batch processing?
 Tony Dip |
Tony Dip, process manager, thermal processing systems, Tokyo Electron America, Austin, Texas
As silicon-based semiconductors approach and surpass the 25nm technology node in a decade or so, one obvious factor that will permeate the semiconductor industry will continue to be manufacturing cost. One of the primary responses to this issue has been substrate scaling. It is generally expected that the next step-up on substrate size will occur around 2015 and result in 450mm (17.7-in.) substrates; this transition will present special problems for thermal processing.
A second important factor that will strongly influence thermal processing is device scaling. Certain MOS device characteristics, such as STI trench depth and MOS gate-electrode height, are expected to remain relatively constant over the next decade or so, yet be packed more tightly together. Scaling also will dramatically increase effective substrate surface area. The anticipated change in direction regarding transistor architecture — going hand-in-hand with scaling — will also play a role in the evolution of thermal processing.
The role of transistor architecture. What next-generation device will supplant today's MOSFET in the next decade or two? The short answer is maybe none. The traditional 2D MOSFET has enough life left in it and is compelling enough from a manufacturing perspective that innovative device and design solutions to the tricky power-consumption and speed challenges will be found. For example, exotic substrates featuring silicon-on-insulator and/or strained Si will move into mainstream production as substrate manufacturing yields improve and production volumes increase. In another example, shallow-channel engineering will come to rely more on in situ doped epitaxial films rather than implantation and spike annealing.
There are also device wild cards, such as folded-channel 3D FET structures (FinFETs and the like). Beyond those are quantum-effect devices that work at the very level of the electron, but pose great design and operational challenges.
From a materials perspective, these changes could involve metal gates or full silicides of poly Si, medium- to high-k gate dielectrics, selective epitaxial Si and SiGe everywhere, and a new generation of engineered sidewall dielectrics, just to name a few. Since the effective substrate area will continue to grow in an exponential fashion, aspect ratios of device features will also increase; thermal budgets for diffusion and CVD process will likely become much tighter; and novel substrate technologies will probably become more common, thus limiting maximum processing temperatures.
Single-wafer technology generally addresses thermal budget and CoO issues via high deposition rates, but it does so because CVD processes are operated in the mass transport regime, and are not generally reaction-rate limited. This typically causes film conformality issues and pattern loading effects. On a similar note, rapid thermal annealing (RTA) will not be possible for strained layer devices due to strain relaxation, and dopant activation below 800°C is simply not effective for many reasons. LPCVD batch processes, on the other hand, manage the deposition issues well, but for many processes have real problems meeting low thermal-budget requirements. What might processing look like in 10 or 15 years? In short, mini-batch (small-batch; 25–50 wafers, one or two wafer lots) or micro-batch (5–20 wafers).
Mini- and micro-batch processing. Balancing and optimizing cost, cycle time, and processing capability, mini-batch offers a good solution for advanced 300mm and 450mm processing for several reasons. A small number of wafers, say between five and 50, can be spaced out enough where pitch is not a concern on across-wafer uniformity. Hot wall processing is inherently stable from a temperature perspective, and because LPCVD processes are reaction-rate limited, excellent uniformity and conformality can be achieved as long as one accounts for gas-phase reactant depletion. Additionally, batch systems can be proportionally purged at volumetric rates similar to other technologies so advanced thin-film deposition techniques, such as atomic-layer deposition, can be employed with ease.
Other mini-batch enabling technologies are already available or are on their way. Among these are integrated plasma generation enabling ultralow temperature processes, including radically diffused oxides, heater cores with fast settling times and wide dynamic operating ranges (50–1000°C), and built-in chamber self-cleaning and autoregeneration capability. These features also will permit sequential operations so film stacks that once required multiple systems or clustered chambers will be feasible within one chamber.
Certainly, large-batch (75–200 wafers, 3–25+ wafer lots) and single-wafer processing will continue to be important in manufacturing, even beyond 2015. Users will want the best solution for their thin-film requirements, one that offers the needed capability at the lowest cost. For many commodity films, large-batch will be preferred just as single-wafer is for dopant activation. A third processing option, mini-batch, will come into its own as a major market segment, and users will have a choice because they can expect every major FEOL semiconductor capital-equipment maker to offer a small-batch option.
Contact Tony Dip at Tokyo Electron America, 2400 Grove Blvd., Austin, TX 78741; ph 512/424-1000, e-mail [email protected].