Precision thickness control in the ECES process
11/01/2004
The electrochemical etch-stop (ECES) technique is a popular method for bulk micromachining of a p-n junction silicon wafer in microelectromechanical (MEMS) applications because it has the ability to fabricate microstructures and membranes with precise thickness control. Studies have reported the fabrication of a silicon microstructure using ECES, but for industrial mass production, the applied potential should be considered thoroughly with respect to the passivation potentials of p- and n-type silicon wafers. The major challenge is in maintaining a sufficiently anodic potential to passivate the n-type silicon over the entire wafer, while simultaneously keeping the p-type silicon at a potential below its passivation potential (i.e., the potential required to cause etching by such etchants as a KOH:H2O solution) [1–2].
The ECES process etches the p-type substrate, leaving the remaining n-type membrane as a sensor material for manufacturing MEMS devices. Consequently, the applied potential should be higher than the passivation potential of n-type silicon (Vpp-n) and lower than the passivation potential of p-type silicon (Vpp-p). An I-V scan test is performed to predict the applied potential window for the p-n junction epitaxial wafer in a KOH solution for the ECES process.
Since the passivation potentials of the p- and n-type silicon wafers are very close in value, the applied potential is a crucial parameter in the p-n junction ECES process. The experiment described here measures the passivation potentials of p- and n-type silicon 4-in. wafers in a 30wt% KOH solution at different temperature conditions: 70°C, 80°C, and 90°C, respectively.
Experimental process
An I-V scan test was performed in a semiautomatic type of etch system manufactured by Grand Plastic Technology Corp. (GPTC).
The p-n junction 4-in. epitaxial wafer has an n-type epitaxial layer (resistance = 5–8Ω-cm; orientation = (100)) that was grown on a p-type silicon substrate (resistance = 1–10Ω-cm; orientation = (100)). In addition, the n-type silicon epitaxial layer was heavily doped to make an ohmic contact with aluminum to serve as an electrode contact, and then connected to a potentiostat.
The electrode contact area is opened up on the n-type epitaxial layer to apply anodic voltage; its resistance should be small enough not to interfere with the silicon and KOH etchant-solution interface potential.
Meanwhile, those wafer surfaces that were not to be etched were protected from the KOH solution by a special wafer holder; those portions of the wafer surface that were supposed to be etched, were directly exposed to the KOH solution. A potentiostat was used to control the applied potential of the silicon wafer (working electrode) with respect to a reference electrode (standard hydrogen electrode; SHE), while a 4-in. circular shape of platinum network acted as a counter electrode.
The I-V test data for both n- and p-type silicon wafers were collected by the on-line monitor computer connected to the potentiostat. An in-line heater controls the temperature of the KOH solution to within ±0.1°C. In the I-V scans, the potential applied to the silicon wafer was scanned from -1.5V~+0.5V, typically at a voltage scan rate of 5mV/sec.
Results
Figure 1 shows I-V curves of the n- and p-type silicon wafers tested at 70°C, 80°C, and 90°C using a 30wt% KOH solution. The passivation potentials of the n-type silicon wafer were -0.64V, -0.5V, and -0.4V, respectively; those of the p-type silicon wafer were -0.45V, -0.4V, and -0.34V, respectively.
 Figure 1. I-V curves of n- and p-type silicon wafers tested at 70??C, 80??C, and 90??C in a 30wt% KOH solution. |
The data show that the passivation potentials for n- and p-type silicon wafers shift cathodically with decreasing temperature of the 30% KOH solution. In addition, the applied potential window is increased as temperature is decreased. Results of the experiment are in accordance with expectations [1]: At a given concentration of KOH solution, as the temperature is lowered, the applied potential window will be increased.
Temperature variation effects
The passivation current densities for an n-type silicon wafer under the experimental conditions (70°C, 80°C, and 90°C; 30wt% KOH solution) are 2.71mA/cm2, 5.41mA/.cm2, and 12mA/cm2, respectively. The passivation current densities for a p-type silicon wafer under the same conditions are 3.93mA/cm2, 7.21mA/cm2, and 12.47mA/.cm2, respectively. Variations in temperature have a distinct effect on passivation current density.
 Figure 2. Current vs. time at the applied potentials of -0.55V and -0.6V in the ECES process. |
Figure 1 shows that the applied potential window for the ECES process of the p-n junction silicon wafer at 70°C using a 30wt% KOH solution is -0.46V to -0.63V (SHE). Based on the I-V curves obtained from the experiments previously described, two candidate applied potentials, -0.55V and -0.6V, were selected for the ECES process of the p-n junction wafers at 70°C using a 30wt% KOH solution. The current vs. time curve was recorded under individual applied potential conditions. Figure 2 illustrates the current monitored for the ECES processes at applied potentials of -0.55 and -0.6V.
Analysis details
The KOH-ECES curves can be divided into three steps. In the first step: the current values are very small and remain stable for a long time, representing etching at the p-type region. Second, the current increases very sharply, forming a current peak that represents the etching process at the p-n junction. Finally, following the current peak, a passivation reaction takes place on the n-type membrane and forms a passive film to stop etching (i.e., the current becomes very small).
A higher peak current was measured at the applied potential of -0.6V than at -0.55V; therefore, the etch rate at -0.6V was greater. The n-side, at an applied potential of -0.6V, is more aggressively etched by the KOH solution than when the applied potential is -0.55V. At -0.6V, the current cannot be promptly lowered at the third step to reach the etch-stop point; thus, the etching process at the applied potential of -0.6V was terminated by removing the wafer from the etch tank.
 Figure 3. OM photo of the wafer surface after the ECES process. |
In the ECES process, the etching is stopped (or the wafer is passivated) when silicon dioxide (SiO2) is formed on the surface. At an applied voltage of -0.6V, the n-type silicon is not more anodic than its passivation potential — at least not such that it can be determined accurately. There is still an etching phenomenon on this n-type membrane because the passive film is not stable enough to withstand the KOH solution. At the applied potential of -0.55V, however, the n-type silicon is more anodic than the n-type passivation potential and can generate a more stable passive film that protects the n-type membrane from being etched by KOH. Consequently, the thickness control of the n-type membrane at an applied potential of -0.55V can reach within ±1µm. Figure 3 is an optical microscope (OM) photo of the n-type membrane fabricated with the ECES technique.
The ECES technique uses a p-type substrate with an n-epi layer, tightly specified for thickness and resistivity. During the etch process, the wafer is immersed in the KOH etchant, and a controlled potential is applied between the n-epi layer of the wafer and the etchant, making the p-n junction act as a reverse-biased diode.
In the reverse-biased mode, the diode prevents the KOH from being exposed to any current, and the KOH performs a normal anisotropic etch through the p-type substrate until it reaches the p-n junction. Then, because the p-type silicon has been etched away, the KOH is exposed to the applied bias, and a reaction forms a passivation film (SiO2) to stop the etching. The membrane thickness is therefore unaffected by the etching time; instead, it is necessary to ensure that the wafer is controlled by an accurate applied potential.
The selection of an accurate applied potential for the ECES process allows more precise thickness control of the n-type membrane, which results in a narrow range of device parameters to be calibrated.
Conclusion
Although the I-V scan method for measuring the applied potential window has been studied in many articles, a systematic integration of the testing procedure, the wafer spec, and the database of an applied potential window for a practical ECES process are all lacking.
This study established the reference of applied potential windows for the ECES process at different temperatures using a 30wt% KOH solution. The applied potential windows for p-n junction wafers at 70°C, 80°C, and 90°C using this solution are -0.45~-0.64V, -0.40~-0.50V, and -0.34~-0.40V, respectively.
The relationship between applied potential and the ECES process has been demonstrated in the experiments described. In the ECES mass production line, establishing a correct applied-potential windows database for different wafer specifications is very important because the running cost and products' quality rely on stringent process-parameters control.
References
- V.M. McNeil, S.S. Wang, K.-Y. Ng, M.A. Schmidt, Digest 1990 Solid-State Sensor and Actuator Workshop, IEEE, pp. 92–97.
- H.A. Waggner, "Electrochemically Controlled Thinning of Silicon," Bell Systems Technical Journal, pp. 473–475, March 1970.
David Ming-Jer Hsu is an R&D process researcher in the R&D department of Grand Plastic Technology Corp., No. 13, Ta-Tung Rd., Hsinchu Industrial Park, Taiwan 303, R.O.C.; ph 886/3-5972353 ext. 273, fax 886/3-5972370, e-mail [email protected].
Yuan-Hsin Li is an R&D director at GPTC.