Issue



Engineered substrates require strain metrology


11/01/2004







Innovative materials have emerged as an alternative to simple scaling for achieving improved device performance [1]. Among the solutions, engineered substrates — in particular, strained silicon-on-insulator (sSOI) — are commonly identified as the most promising in improving the Ion/Ioff ratio and transconductance [1–3]. Because strain is the major component in this technological breakthrough, there is a need to develop an experimental technique to measure strained layers and a methodology to monitor it. Fabrication of sSOI wafers is reviewed together with techniques used to monitor strain. Strain measurements obtained on donor wafers and on the finished sSOI structures are presented in this article.

The continued shrinking of conventional CMOS devices to achieve enhanced performance has revealed limitations such as gate-oxide tunneling, carrier-mobility reduction by high-k gate dielectric, heat dissipation, and so on. One solution, sSOI, combines the performance and scalability of fully or partially depleted SOI and the mobility enhancement of strained silicon. Its attractiveness is reinforced by its compatibility with CMOS integration processes, standard MOSFET architectures, and circuit layouts. The biaxial tensile strain in sSOI changes the silicon band structure and may also affect the silicon surface microroughness [4–6]; these changes lead to higher mobility of charge carriers.

Production of sSOI wafers starting from relaxed SiGe virtual substrates is discussed here, and SiGe relaxation mechanisms are also reviewed to illustrate some of the issues encountered when making strained silicon layers. A review and comparison of potential experimental techniques that can be used to monitor strain during wafer and device realization also is given. Results obtained by various techniques on donor wafers such as strained-Si-on-SiGe virtual substrates, and on the final structures such as strained-silicon-on-SiGe-on-insulator (SGOI) and sSOI wafers, are discussed along with the potential impact of strain fluctuations on carrier drift mobility and device performance.

Engineering sSOI and SGOI substrates

Today, Smart Cut technology is used by Soitec for high-volume production of SOI wafers [7, 8]. Atomic species (preferably hydrogen ions) are first implanted in a donor substrate A. This step induces the formation of a weakened zone below and parallel to the wafer's top surface. Next, substrate A is bonded to a support wafer B. Prior to the bonding step, an insulating layer such as SiO2 is formed on at least one of the two wafers. The splitting step that follows, which takes place inside the weakened zone, gives rise to the transfer of a thin layer from substrate A onto the support B. Finally, a treatment can be performed to eliminate the roughness left after splitting. The process is suited for manufacturing SOI wafers, especially for thin top silicon layers (<500nm) with very high silicon thickness uniformity. It also allows great flexibility in layer thickness for the buried oxide — with values ranging from a few microns down to <100nm.

A layer transfer technique can be used to obtain tensile sSOI wafers. In this case, the starting material is an epitaxial layer stack, ending with relaxed SiGe, on top of an intermediate strain-relaxed buffer layer (for instance, a thin strain-relaxed buffer or a graded buffer) [9]. Using hydrogen implantation in the relaxed SiGe layer, the top part of this epitaxial stack is transferred onto another silicon substrate. An insulator (preferably silicon dioxide), obtained through thermal oxidation or deposition on at least one wafer before bonding, enables the formation of a structure with a buried dielectric.

Two approaches based on this technology are used to manufacture SGOI and sSOI. In one approach, a relaxed SiGe-layer-on-insulator a few hundred angstroms thick is formed by layer transfer. A strained Si layer is subsequently grown on top of it. In this case, known as SGOI, the total semiconductor layer thickness at the end of the process (strained Si + relaxed SiGe) is adjusted typically in the 300–700Å range. SGOI substrates are well adapted for partially depleted SOI architectures.

In the second approach, the tensile-strained silicon is grown directly on the donor wafer (i.e., on the relaxed SiGe layer). A bilayer containing the strained Si and the relaxed SiGe is then transferred onto the handle Si substrate. After the removal of the SiGe layer, for example, through a selective wet etch step [1, 10], the tensile-strained Si layer is exposed, forming sSOI. This second approach addresses the needs of fully depleted SOI architectures.

Relaxed SiGe in SGOI provides a means for changing the lattice parameter of the top silicon layer, and therefore enhancing its electrical properties. An sSOI wafer that contains only silicon and oxygen may be adopted more rapidly in IC manufacturing. Ge-containing wafers require a lower thermal budget because of the risk of Ge diffusion, propagation of misfit dislocations from the strained Si/SiGe interface, and Ge cross-contamination. Regardless of whether SiGe alloys are used in the final product, it is important to study the behavior of this virtual substrate because it directly influences the quality of the resulting strained Si and sSOI wafer.

SiGe relaxation

Cost-effective production of sSOI wafers requires growing SiGe films with a high crystalline quality, a high degree of relaxation, and high throughput (low cost). These three requirements are not yet simultaneously met, so a cost/quality tradeoff is typically accepted. Silicon-germanium films are produced by heteroepitaxial deposition on Si or Ge substrates, and the mismatch between the Si and SiGe lattice parameters is accommodated mainly by two mechanisms [11]. Relaxation of the atoms in the deposited layer to their natural lattice spacing produces periodic undulations of the SiGe surface, forming a pattern known as crosshatch. Two examples of a crosshatched SiGe surface are shown in Fig. 1.


Figure 1. a) An AFM image (40??40??m field) and b) an optical profilometer image (90??120??m field) of a relaxed Si.8Ge.2 thin film, showing crosshatch surface undulation with roughness of 15?? (rms).
Click here to enlarge image

The first stage of SiGe relaxation occurs at an elevated temperature, when the SiGe layer is just slightly thicker than the critical thickness. Sixty-degree misfit dislocations are nucleated and propagate along the <110> crystalline directions, which correspond to the intersection of the <111> gliding (or slip) planes with the <100> wafer-surface and induce-surface steps aligned along the same <110> crystalline directions. These steps of atomic dimensions arise from single or multiple dislocations aligned along a single slip plane. Further increases in film thickness result in rapid strain relaxation through the introduction of additional misfit dislocations. According to the model of T. Spila et al. [11], the step multiplication is accompanied by an increase in the SiGe growth rate due to a decrease of the H surface coverage. The resulting undulation of the SiGe surface is accompanied by short length scale variations in the strain field. This strain field inhomogeneity may be observed experimentally if the resolution is smaller than the crosshatch length scale.

Characterization of strained Si

Strained Si can be characterized using traditional thin-film methods for thickness and composition, but the direct quantification of stress, strain uniformity, and evolution of that stress in response to subsequent CMOS processing is not readily available. Among the many techniques available for stress metrology, x-ray diffraction (XRD) and Raman spectroscopy are the most promising. Photoreflectance also holds the potential to probe strain and is being investigated. XRD is the only technique that can directly image the crystalline lattice, and it has been used to measure composition and the residual strain in SiGe layers [12–14]; however, it is time-consuming, has limited spatial resolution, and becomes challenging when applied to thin and/or bonded layers.

Raman spectroscopy

Raman spectroscopy has been used to measure stress in cubic semiconductors and especially in silicon layers [15] by probing the optical phonon shifts [16–19], which are directly related to the stress or strain applied to the crystal. Raman spectroscopy benefits from high spatial resolution and throughput. With appropriate choice of laser wavelength, layers at different depths from the surface can be selectively probed. The shorter wavelength of a UV laser looks mostly at the first 10nm, which is ideal for thin SOI layers [20, 21]. From Raman peak positions, one can also determine the composition and the residual strain of SiGe alloys. We have used one of the analysis methods described by J.C. Tsang et al. [22], which is based on the measurements of the three different Raman modes related to the Si-Si, Si-Ge, and Ge-Ge bonds. The frequency of these three modes directly depends on the Ge content and the strain of the SiGe layers through the following relationships:

ωSiSi = 521 - 68x - 815 ε//(1)
ωSiGe = 399.5 + 14.2x - 575 ε//(2)
ωGeGe = 282.5 + 16x - 385 ε//(3)

where x is the germanium fraction in the Si1-xGex alloy and ε// is the in-plane strain. These coefficients were determined experimentally and calibrated with HRXRD and SIMS measurements [22, 23]. We use relationships 1 and 2 to calculate the Ge content and to derive the degree of relaxation:

Click here to enlarge image

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where ε//exp is the residual strain measured and ε//th is the theoretical strain of a fully relaxed SiGe layer having a composition x of Ge.

Raman mapping was performed on a strained Si/SiGe structure to crosscheck with published results and to calibrate the relationships used. The investigated layer stack is drawn in Fig. 2, together with the observed Raman spectrum. Many such spectra were collected using a tightly focused beam that was stepped in 1µm increments to produce gray-scale or color-coded maps of 40×40µm regions [24]. The peaks associated with Si-Ge and Si-Si bonds of the SiGe film shift coherently upward and downward depending on the position on the sample; from this we infer that the origin for this variation is related to the strain variation in the SiGe layer.

Click here to enlarge image

Figure 2. In the Raman spectrum of a strained Si film grown on SiGe, phonon modes corresponding to the Si-Ge (400cm-1) and the Si-Si (508cm-1) bonds are observed. The strained-Si film signal is a shoulder on the high-frequency side of the unstrained Si-Si peak. (Sharp spikes correspond to the plasma lines of the argon laser.) A 40×40µm area map is shown for each phonon peak, in which the local contrast depends on the Raman shift of that peak as a function of position on the sample.

From the Raman shifts, we can directly determine the stress of the strained Si layer and the composition and degree of relaxation of the SiGe layer. From the SiGe composition and residual strain, we can then derive the SiGe lattice parameter and the stress it must induce in the Si cap. The strain field observed in the Si cap is aligned with the <110> crystalline directions, just like the crosshatch and the misfit dislocations network, and it originates from a spatial variation of the relaxation of the SiGe layer.


Figure 3. The Raman map of SGOI exhibits the same strain-network pattern in the transferred SiGe layer and in the strained Si cap grown on it. Stress in the bulk Si substrate is low and uniform.
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The Raman map of SGOI and sSOI exhibits the same strain-network pattern in the transferred SiGe layer and in the strained-Si cap grown on the SiGe layer. An example for SGOI is shown in Fig. 3. By performing the analysis of the Raman shifts, we deduced the composition and degree of relaxation of the SiGe. The difference between the predicted and measured stress is <100MPa and it shows lattice-matching between the SiGe and the strained Si films.


Figure 4. Micro-Raman: Stress in an sSOI sample is preserved after a 2 hr anneal at 1100°C. A vertical bar on the right shows the stress scale in MPa.
Click here to enlarge image

CMOS processing will require induced strain to remain intact through several thermal cycles. To demonstrate the robustness of the sSOI material, a sample was heated for 2 hr at 1100°C in a conventional furnace. The strain measured by Raman spectroscopy following this slow thermal treatment is shown in Fig. 4. The amount of strain is almost unchanged, indicating that the strained Si/SiO2 interface provides very strong bonding.


Figure 5. Large length-scale Raman map (10???~6cm) of an sSOI surface shows a high degree of stress uniformity (mean stress value = 1.5GPa, ????? = 65MPa). Measurement points are 5mm apart. A vertical bar shows the stress scale in MPa.
Click here to enlarge image

It is also possible to create a more macroscopic picture of the stress uniformity on an sSOI wafer by comparing the Raman mode shifts from adjacent regions. Figure 5 is a color rendering of the stress in a 10×6cm area of an sSOI wafer with a mean value = 1.5GPa and a standard deviation σ = 65MPa.

Conclusion

Micron-scale investigation of the strain in SiGe and strained Si films reveals a small strain modulation aligned with the <110> crystalline directions. Raman spectroscopy is well suited for exploring strain behavior of thin-film materials because of small spot size, control of depth sampled, and speed. Transferring strained Si to create sSOI or SGOI using Smart Cut technology maintains stress, even after heating to high temperature for long periods of time. Such results open a wide area of study and bring closer the adoption of next-generation engineered materials.

Acknowledgment

Smart Cut is a trademark of S.O.I.TEC Silicon on Insulator Technologies.

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Mark Kennard received his PhD in chemistry from Northwestern U. and is the process development manager in the advanced technology department at Soitec, Parc Technologique des Fontaines, 38190 Bernin, France; ph 33/4-38-92-17-70, e-mail [email protected].

Ian Cayrefourcq received his PhD in microelectronics from the Institute of Electronics and Microelectronics of Northern France and is the new technology development department manager at Soitec.

George Celler received his PhD in solid-state physics from Purdue U. and is chief scientist at Soitec USA.

Carlos Mazuré received two doctorates in physics from the U. of Grenoble and the Technical U. of Munich, Germany. He is the CTO at Soitec.