Technology News
10/01/2004
MEMS technology enables low-cost mini-SEM
Researchers from Horiba Ltd., Ulvac Inc., and Tokyo U. have developed a shoe-box sized scanning electron microscope that seems inexpensive to make, and uses low voltages that should not damage or build up charge on sensitive materials. Keys to this mini-SEM are an e-beam column of electrostatic lenses made with MEMS technology directly inside a ceramic cylinder roughly the size of a fountain pen, and an electron gun integrated into a miniaturized high-vacuum ion pump.
 Figure 1. Small-scale scanning electron microscope uses ceramic column with integrated electrostatic lenses made by MEMS technology. Total tool height: 33cm. |
The proof-of-concept prototype is getting 60–30nm resolution, with 1kV acceleration voltage and 10pA beam current. Work is now underway using the initial data to improve the optical column design, aiming at the 10nm resolution achieved by a large-scale SEM. With improved resolution, this low-cost, 30cm SEM could be used to check for defects at each step of the production process in the fab, or even taken into the high-school science classroom.
 Figure 2. Proof-of-concept tool gets 60–30nm resolution, with 1kV acceleration voltage, 10pA current. Shown is gold mesh with 63.5µm pitch. |
MEMS technology provides the precision processing and assembly necessary to make the smaller and more effective electrostatic lenses. Ceramic powder is pressed into a mold and fired, making trenches circling the inside of the cylinder for the dielectric areas. The inside of the tube is then polished, and the raised rings remaining between the trench rings are plated with gold for the lens electrodes. Vias through the tube's walls connect the inner electrodes with the outside of the cylinder and the rest of the tool. External diameter of the tube is 12mm; internal diameter ranges from 3–6mm in different areas; and internal features range from 0.7–1.5µm.
To get the high vacuum required for the thermionic field emission source that limits chromatic aberration, researchers developed an electron gun integrated inside a miniature ion pump. The ion pump and its cylindrical magnetic field encircle the electron gun, and the gun is further shielded by surrounding displacement cells and permanent magnets, leaving essentially no magnetic field effects in the center of the unit. The pump produces a vacuum of 7×10-8 Pa, with displacement of 1.5liters/sec.
Katsuya Okumura, Tokyo U.; Motosuke Miyoshi, Tokyo U.; Yutaka Saijo, Horiba Ltd.; Shigeru Amano, Ulvac Inc., and SST partner Nikkei Microdevices
IMEC launches three-pronged effort to replace embedded SRAM
The IC industry is facing a major cache crunch. Embedded memory requirements for next-generation processors and system-on-chip (SoC) designs are expected to push far beyond the feasible limits of the venerable six-transistor SRAM and today's nonvolatile flash EEPROM technologies. Looming technical barriers in future device shrinks and the need for greater on-chip cache storage have resulted in more than a dozen development efforts across the industry to find suitable replacements for embedded SRAM and flash.
And now comes a new three-pronged R&D program at the IMEC research organization in Leuven, Belgium. IMEC hopes to attract four or five integrated device manufacturers (IDMs) to help define new embedded RAM concepts for second and higher levels of on-chip cache in logic ICs at the 45nm and below process nodes. IMEC's "eRAM" program is pursuing three embedded memory concepts: direct tunneling RAM; ferroelectric field-effect transistor (FeFET); and a floating body cell, which would be made with silicon-on-insulator (SOI) substrates and, possibly, 3D FinFET device structures.
IMEC researchers have already produced some of the first demonstration devices for these memory concepts, and they plan to present analysis data from the experimental circuits at the 2004 IEEE International Electron Devices Meeting (IEDM) in San Francisco in mid-December. IMEC soon will begin making memory arrays based on these devices. Analysis data on the performance of these prototypes will be released in 2H05, says Ludo Deferm, IMEC VP of business development.
"All three concepts will not likely be used. Each one has potential advantages and challenges," Deferm says. "SRAM has not been replaced by something else because it can be added to logic with no additional processing steps. Therefore, it has been fairly cheap and only a design issue." But SRAM does cost in area, notes Deferm, referring to the standard six-transistor cell design that has served as embedded memory in logic ICs since the 1980s. "SRAM becomes more expensive as embedded memory grows. So perhaps there is a window to reduce the area of memory but at slightly higher processing costs."
IMEC's eRAM program aims to distinguish itself from other embedded memory projects by tackling the three different concepts in parallel and leveraging the research group's ongoing work in high-k dielectrics. High-k materials will be applied to the direct-tunneling RAM and FeFET memory concepts to help reduce operating voltages, improve performance over time, and ensure reliability. Meanwhile, the floating body cell concept takes a more radical design approach and uses SOI wafers. IMEC says the floating body cell technology will be implemented with planar as well as 3D FinFET transistors.
Double-gate FinFETs have been proposed in recent years as a potential solution for reducing leakage in transistors while they are in the off-state. In a FinFET, a channel region is sandwiched between two gate structures that form vertical "fins" in the third dimension. The double-gate structure should make it easier to shut off current flow in the channel and avoid leaky transistors.
"The FinFET presents a special situation. It provides more control [of stored charges for bits] than normal MOS devices, but it will have to wait until transistor designs change and SOI becomes standard in CMOS production," Deferm says. "I don't think that will happen at the 45nm node, but it could in 32nm or beyond."
In the floating body cell project, preliminary retention results, obtained on partially depleted SOI-based MOSFETs programmed by impact ionization, show the memory effect in scaled-down SOI technology (see Fig. 1).
Meanwhile, one of the other two concepts might find its way into 45nm logic devices, if IMEC's three-year eRAM program is successful in quickly identifying a replacement for today's embedded memory technologies. A prime target for the technology will be processors and SoC designs that require large amounts of cache memory. In some cases — especially for cell phones and wireless applications — the die area of logic devices could be 80–90% memory. IMEC's project aims to create an embedded memory cell that is at least half the size of a six-transistor SRAM.
Similar to an EEPROM cell, the direct-tunneling RAM will use a very thin (~1.5nm) oxide flash structure in which a charge can be stored on either a floating gate or on a charge-trapping layer. "The difference [from today's flash EEPROM] is that we place high-k materials between the storage gate and channel," Deferm says. The high-k film could enable the direct-tunneling RAM to operate at lower programming voltages while maintaining SRAM-like steady performance over time and tens of thousands of write/erase cycles. IMEC said first simulation results of the tunneling model show the feasibility of a 10 nsec programming time at the 45nm process node (Fig. 2).
 Figure 2. Modeling results for a direct tunneling device showing 0.5V of read window for a 10nsec write access time, based on IMEC's model. |
In IMEC's FeFET memory concept, researchers are applying ferroelectric material on top of a high-k buffer layer. They aim to use high-k materials between the FET's channel and ferroelectric structure to lower programming voltages. FeFETs have recently gained a lot of attention because they can be more easily scaled than today's capacitor-based ferroelectric RAMs, according to IMEC.
"In the initial phase of the program, we are working on transistor concepts, showing if they are reliable, reproducible, and functioning as expected," Deferm explains. "In the second phase, we will make arrays and look at reliability issues as well as interactions between cells. At this moment, we're not sure which kind of high-k materials will be used and if it will be reliable. Introducing something new with high-k material for a memory architecture will require iterations in both processing at the device level and with materials.
"At this moment, we are working heavily on 45nm node," he adds, referring to IMEC's R&D programs in transistor stacks and new materials. "If production is targeted for 2009, the companies will want to start their own development with full specs around 2007. That means we must be ready [to deliver R&D results] around the end of 2006 for the 45nm node." — J.R.L.