Issue



SOI wafers: Fabrication techniques and trends


10/01/2004







Introduced as an alternative CMOS technology in 1978, silicon-on-insulator (SOI) offered the potential for high speed, low power consumption, soft-error reduction, latch-up immunity, manufacturing process simplification, and improved scaling. While SOI material was initially used in small niche markets, the opportunity for mainstream use has significantly broadened. During the last few years, it has serviced a variety of leading-edge IC applications such as microprocessors, servers, smart power, and RF signal processors, typically with partially depleted (PD) silicon layers.

With MOS transistor scaling of the physical channel length (Lg) to the sub-50nm regime — en route to the sub-10nm regime — alternative CMOS device structures [i.e., fully depleted (FD) ultrathin body], in conjunction with multiple gate configurations such as the FinFET with high-k gate dielectrics, metal electrodes, elevated source-drain, and strained silicon channels, will significantly broaden the opportunity for mainstream utilization of SOI [1].

Fabrication methods

The fabrication [2] of SOI wafers has proceeded via two main routes. The first was the implantation of oxygen into the polished silicon or epitaxial silicon wafer, explicitly denoted as the separation by implantation of oxygen into silicon (SIMOX). A related improvement to the SIMOX method, especially for low-dose oxygen implants (≈1017cm-2 SIMOX products) was accomplished by annealing in an oxygen ambient. SPIMOX, a recent variant to the SIMOX methodology, has used water plasma species during the implantation process, including H2O+, HO+, and O+.

The second major route for SOI fabrication has been generically described as the bonded wafer approach. As the name implies, two wafers are bonded together via the thermally grown silicon oxide (SiO2), for example, on the first wafer. One subsequently separates the two wafers, resulting in a thin silicon layer (on SiO2) from the first wafer being transferred to the top of the second wafer, the latter often referred to as the handle wafer.


Smart Cut technology process flow (courtesy of A. Wittkower and Soitec, USA) [3]. Reproduced with permission of The Electrochemical Society Inc.
Click here to enlarge image

Many fabrication and separation methodologies have been developed for the bonded wafer approach. These include macroscopic grinding or etching back of the silicon wafer until achieving the desired film thickness. A more sophisticated approach has been to place, before wafer bonding, an etch-stop mechanism in the silicon wafer to be thinned. The faster removal of the bulk of the first wafer proceeds by a selective etchant, terminating upon reaching a heavily doped boron layer, a Si:Ge epitaxial layer or some combination of Ge-B.


This approach is referred to as the bond-and-etch SOI (BESOI) process. An additional mechanism of removing the bulk of the first wafer is by a process referred to as plasma-assisted chemical etching (PACE). The procedure relies on a high-speed mapping of the SOI layer thickness followed by scanned plasma etching, which selectively etches the thicker areas of the surface to provide the requisite SOI layer uniformity.

An additional variant of the bonded wafer approach is referred to as the Smart Cut process (see figure) [3]. In this procedure, the silicon layer [and the buried oxide (BOX) thickness] in the final SOI wafer is split off from the original starting wafer and transferred onto the handle wafer.

Proceeding with the transferred layer approach, one may also consider the epitaxial-layer transfer (ELTRAN) approach. This methodology is an improved and updated application of the process initially referred to as full isolation with porous oxidized silicon (FIPOS). A porous film is anodically formed by an electrochemical reaction. The porous silicon is mechanically weak, but preserves the single crystallinity of the original silicon for subsequent SOI processing. After sealing the pores at the surface by a high-temperature anneal in H2, an epitaxial layer is grown on top of the porous silicon prior to subsequent SOI processing.

Other layer transfer approaches may also be used, such as the fabrication of strained silicon layers on SOI, a particularly advantageous advanced device configuration combining the high-mobility features of strained silicon with the advantages of SOI. These configurations are achieved by layer transfer techniques to facilitate the strained silicon directly on the insulator (sSOI), with both PD and FD configurations. SIMOX procedures for strained silicon have also been noted; there may be additional process issues associated with the 1300–1350°C SiOx anneal.

The previously described fabrication procedures each have specific benefits and detrimental effects, the latter often exacerbating the cost and yield issues associated with the SOI approach. The additional cost incurred by bonding two wafers to form an SOI configuration can be reduced using techniques that allow one of the original wafers to be recycled a number of times (see figure).

Additional historical methods include silicon-on-sapphire (SOS), silicon-on-zirconia (SOZ), and a host of recrystallization procedures from a liquid melt. Other techniques have also included epitaxial-layer overgrowth (ELO); the large-grained silicon crystallites produced were not necessarily unsatisfactory in device performance and solid phase epitaxy (SPE).

SOI film thickness trends

The trend for leading-edge applications is FD SOI configurations that require a top thin silicon layer (<30nm). In most cases, some degree of removal of the silicon layer appears to be necessary for today's SOI products. That is, one often obtains a PD structure and then thins the incoming silicon layer to the desired FD thickness for the specific application. The decreased thermal conduction due to the BOX layer also requires notice.

For single-gate FD SOI devices, the BOX thickness scales with gate length, although the optimal thickness of the BOX continues to be addressed [4]. Considerations of BOX capacitance, circuit heat dissipation due to decreased thermal conduction, gettering, electrical integrity, wafer manufacturing capabilities, metrology, wafer quality and cost, and yield drive the choice of the BOX thickness value. For PD SOI devices, however, the BOX thickness has less impact on device parameters and may be expected to remain between 100–200nm. It is expected that it will be difficult to maintain the PD operating mode for an SOI CMOS device once the technology generation becomes <~50nm, corresponding to an Lg of 20nm. FD behavior using multiple gates somewhat relaxes the need to thin the BOX and silicon layers [1, 5].

Metrology and characterization

Characterization and metrology for SOI wafers is a significant challenge. One critical example is the assessment of SOI material properties with an edge exclusion of 2mm (per the 2003 ITRS.) The particle-metrology readiness grades listed for polished and epitaxial silicon wafer characteristics may not be generally applicable to SOI wafers. Metrology methods for many of the SOI defect categories call for destructive chemical etching that decorates but does not uniquely distinguish various types of crystal defects. These various defects may not all have the same origin, size, or impact on the device yield, and therefore may exhibit different kill rates. Nondestructive and fast-turnaround methods are also needed to measure electrical properties and structural defects in SOI materials. Finally, metrology issues associated with strain (the rapid spatial variation of strain and Si:Ge composition, the detection of threading and misfit dislocations, and other defects, as well as the measurement of surface roughness) require attention [6].

Prognosis

Planar bulk polished and epitaxial wafers, as well as PD and even FD SOI silicon materials, present short-channel effect scaling issues that become more significant as Lg approaches the 30nm, and especially the sub-10nm, regimes. The relative immaturity of SOI materials compared to bulk and epitaxial silicon, however, will result in significant challenges for the understanding of SOI-specific defects and their impact on device performance and yield in a production environment.

The assurance of continued scaling to the 18nm technology generation (~Lg = 7nm) appears soluble within currently understood physical principles. Effective nonplanar solutions must rectify significant process issues for ultrathin-body transistors in conjunction with multiple-gate and FD SOI, in some combinatorial mix. The applicability of SOI materials for leading-edge IC applications appears warranted with the growth expectations anticipated with Moore's law and the ITRS, especially with 3D device configurations resulting in a potential plethora of unique configurations [7].

The ultimate CMOS MOSFET with Lg<10nm may be a lightly doped channel (strained silicon, or perhaps germanium), ultrathin-body SOI multiple-gate MOSFET (with multiple fins), in conjunction with the high-k gate dielectric, multigate metal electrodes (near mid-gap work function), elevated source and drain, etc. Beyond that regime, an emphasis on alternative novel materials (beyond or in conjunction with Si) and device structural configurations (beyond or in conjunction with CMOS) appears essential.

Acknowledgments

Discussions with Mark Gardner, Larry Larson, Byoung Hun Lee, Daniel Pham, and Robin Tichy are appreciated. Smart Cut is a trademark of S.O.I.TEC Silicon On Insulator Technologies. ELTRAN is a registered trademark of Canon.

References

  1. H.R. Huff, P.M. Zeitzoff, "The 'Ultimate' CMOS Device: A 2003 Perspective," Intl. Conf. on Characterization and Metrology for ULSI Technology, AIP 683, pp. 107–124, 2003.
  2. G.K. Celler, S. Cristoloveanu, "Frontiers of Silicon-on-Insulator," J. Appl. Phys., 93, pp. 4955–4978, 2003.
  3. A. Wittkower, "Some Manufacturing Techniques for Thin Film SOI," ULSI Process Integration II, ECS PV 2001-2, pp. 495–505, 2001.
  4. V.P. Trivedi, J.G. Fossum, "Nanoscale FD/SOI CMOS: Thick or Thin BOX?" submitted to Electron Device Letters, 2004.
  5. H.R. Huff, P.M. Zeitzoff, "An Analytical Look at Vertical Transistor Structures," Solid State Technology, p. 59, Aug. 2004.
  6. M. Bulsara, B. Standley, G. Celler, D. Myers, H.R. Huff, "Sematech Tackles Emerging Materials," Solid State Technology, pp. 50–54, Jan. 2004.
  7. D.A. Antoniadis, A. Wei, A. Lochtefeld, "SOI Devices and Technology," Proc. 29th European Solid-State Device Research Conf., pp. 81–87, 1999.

For more information, contact Howard Huff at International Sematech, 2706 Montopolis Dr., Austin, TX 78741; ph 512/356-3334, e-mail [email protected].