MEMS, head, and packaging applications using through-mask Cu deposition
10/01/2004
Through-mask electrodeposition is receiving increased attention in microelectronic applications. The focus of this work was to develop a new copper bath and process for high-rate deposition, which meets the general process requirements for patterned applications.
Used to manufacture thin-film heads for the data storage industry since the 1970s, through-mask electrodeposition is still being widely adopted to create high aspect-ratio topography in numerous devices including magnetoresistive (MR) and giant magnetoresistive (GMR) heads [1, 2]. It is also being evaluated and adopted to replace traditional bulk and surface micromachining processes in microelectromechanical systems (MEMS) manufacturing [3, 4]. Due to the advent of wafer-level packaging (WLP) technology, through-mask deposition has become widely used to deposit dense wiring structures in a cost-effective manner.
The most common structures formed by through-mask copper deposition are coils and pads for MR/GMR head manufacturing [2]; integrated micro-passives such as inductors and transmission lines for radio-frequency integrated circuits and monolithic microwave integrated circuits [5, 6]; and studs, pillars, and redistribution lines for WLP applications [7–9].
Most through-mask applications require fine-grained, flat, and low-stress deposits at high deposition rates to achieve easy process integration and high productivity.
Experimental conditions
In experiments, 150 and 200mm wafers with a structure of Si(substrate)/SiO2/Ti, TiN, or TiW/PVD-Cu
esist patterns were used. Several types of resist with various feature shapes, open areas, and thicknesses were evaluated, and the Intervia 8540 additive package (from Rohm and Haas Electronic Materials) with three components was used.
Wafers were plated with Semitool's conventional or CFD-type fountain reactors. An EG&G Model 263A potentiostat (with EG&G 270 electrochemical software and a Model 616 RDE motor) was used for linear sweep voltammetry (LSV) and cyclic voltammetry (CV). A focused ion-beam (FIB; FEI Dual Beam 820) tool and a surface metrology tool (Veeco, Dektak 300-Si) were used to analyze deposit properties.
Bath and process development
The following composition was chosen for high-rate deposition after considering the limiting current density (LCD) and stability of baths: 55–65g/liter Cu2+, 70–100g/liter H2SO4, and 70–100ppm Cl-. Wafer-scale tests with patterned wafers showed that deposition rates of 4–5µm/min are generally achievable without the onset of abnormal growths. Various organic mixtures were tested to achieve smooth, flat deposits (shape ratio ≈1) with good adhesion at high deposition rates, where the shape ratio is defined as the ratio of the thickness at the cavity edge to the thickness at the cavity center [10].
Several defects associated with organic mixtures and their concentrations were observed at high deposition rates [11]. Pores and local dendrites were caused by the high surface tension of the bath and local mass-transfer limitation. Irregular surfaces and crater-type defects were thought to result from the uneven adsorption or reaction of certain organic additives on surfaces, and rough surfaces were due to a poor grain-refining effect.
Some organic mixtures produced highly stressed deposits, resulting in delamination. Severely domed or sloped profiles were also observed along the convective flow direction. Many factors affect the current distribution and growth shape of deposits [9–15], but some organic mixtures produced more domed or sloped profiles at the same process conditions.
The Intervia 8540 additive package (three components) was used. The effects of each organic component on the growth shape and surface morphology at 4µm/min are summarized in Fig. 1. Without organic additives, surfaces are rough and faceted, but become smoother with the addition of component A (grain refiner). In conjunction with component B (wetting agent), component A produces much smoother surfaces. As a result of the hydrophobic properties of component C (leveler), this component produces abnormal growths with large nodules and columns in the absence of wetting agents. Surfaces become flat with the addition of component C in the bath. A significant change in shape ratio is also observed with varying leveler concentration [11].
Figure 2 illustrates the macroscopic effect of organic components and their concentrations on the deposition (rate) in cyclic voltammograms. CV shows the change of stripping areas (which is proportional to the amount of Cu deposited) with certain organic additives. With increasing component A (accelerator) concentration in a bath that was strongly suppressed with components B and C, the deposition is significantly reactivated (Fig. 2a). The suppression effect of component B is so strong that a very small addition (for instance, 0.1ml/liter) results in a drastic change of stripping area (Fig. 2b). With increasing component B concentration, the deposition is further suppressed. The suppression effect of component C is much weaker than that of component B (Fig. 2c).
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Effects of mask parameters and process conditions
The maximum achievable deposition rate depends greatly upon mask parameters such as open area and thickness. With increasing resist thickness, the achievable deposition rate decreases due to an increase in diffusion length scale. Due to an increased consumption rate of metal ions with an increase in the open area, a larger open area causes a lower LCD, and thus a lower achievable deposition rate at a given resist thickness.
With increasing current density or decreasing duty cycle (while maintaining the average current density constant), the thickness distribution within a die changes due to the increased influence of the primary current distribution. The fraction of current flowing along the die edge, where the space between dice was much larger than the bump pitch, increases with increasing current density or decreasing duty cycle. This worsens the within-die (WID) thickness uniformity [10, 12]. Component C has a leveling effect on the microscopic feature-scale growths (Fig. 1), but shows no significant influence on the macroscopic pattern-scale thickness distribution.
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When the fraction of LCD is low, the growth shape is not significantly influenced by cavity dimension and mass transfer conditions. With an increase in the fraction of LCD, asymmetric surface profiles are developed along flow direction, and the growth shape varies with cavity size, pitch, and deposit thickness. With a thicker mask, the dependency of growth shape on cavity size becomes more severe due to an increase in diffusion length scale. The shape ratio with pulse current deposition is larger than that with direct current deposition. This is also due to the increased influence of the primary current distribution within the cavity, resulting in a higher LCD at cavity edges [10]. A significant change in shape ratio is observed with varying leveler concentration.
Results achieved with optimized conditions
The process results with optimized conditions meet the general process requirements listed in the table above. The deposition rate can be selected between 2 and 5µm/min (preferably, 3–4µm/min) based upon process specification, open area, mask thickness, and pattern configuration. As the growth shape can be affected by various factors [9–15], the proper waveform that produces flat surfaces may be variable with pattern parameters and mask surface properties. In the cases where direct current produces shape ratios <1, pulse current with moderate duty cycles (≥50%) may be used to improve the surface flatness without severely deteriorating WID thickness uniformity.
Surface roughness and shape ratio were measured with various patterned wafers deposited at 3–4µm/min. Surfaces are very smooth (Ravg <10nm and Rpeak <20nm) with the shape ratio close to 1 (0.9–1.1). Figure 3 shows the growth shape and surface morphology of various deposits without significant dependency of surface properties on feature size and type. The adhesion with underlayers is sufficient to pass the tape-pulling test. Within-wafer (WIW) and WID thickness uniformities for various wafer types are shown in Fig. 4. Uniformity targets are met at 4µm/min with various wafer types (Figs. 4a and b). Twelve wafers were plated at the same condition to see the process repeatability (Fig. 4c). The average WIW uniformity was 9% (3σ) at 4µm/min with a wafer-to-wafer (WTW) thickness repeatability of 2.4% (3σ). Thickness uniformity over bath aging was tested while maintaining bath composition. Over two months and 30A-hr/liter, the average WIW thickness uniformity was 7.5% (3σ).
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Conclusion
A new copper bath and process for through-mask deposition was developed to meet patterned application requirements. Deposition rates of 2–5µm/min (the preferred values of 3–4µm/min may also be chosen) were attained with smooth (Ravg <10nm and Rpeak <20nm) and flat (shape ratio ≈1) deposited surfaces. The adhesion of deposits with underlayers is sufficient to pass the tape-pulling test. WIW and WID uniformity is <10% (3σ and % half-range, respectively) with a WTW thickness repeatability within 3% (3σ). Good process repeatability over bath aging was also demonstrated, where the average WIW uniformity was 7.5% (3σ) up to 30A-hr/liter.
Acknowledgments
The authors would like to express special thanks to Gregor Saveskie at Semitool for his FIB analysis. Intervia is a trademark of Rohm and Haas Electronic Materials.
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Bioh Kim received his BS and MS in metallurgical engineering from Seoul National U. and is a senior ECD process development engineer at Semitool Inc., Kalispell, MT; ph 406/752-2107, fax 406/751-6371, [email protected].
Tom Ritzdorf received his BS in chemical engineering from Montana State U. and his MS in chemical engineering from the U. of Minnesota. He is the director of ECD technology at Semitool Inc.
Stephen Christian is the applications manager at Rohm and Haas Electronic Materials' PFT Division, Freeport, NY; ph 516/868-8800, fax 516/868-4781, [email protected].
Robert Forman is the sales manager at Rohm and Haas Electronic Materials' PFT Division.