Technology News
09/01/2004
Spread of RET masks at 65nm node drives 'virtual stepper' software
Next-generation reticle sets for 65nm ICs will be blanketed with resolution enhancement technology (RET) so that current-generation lithography tools can adequately pattern devices and interconnects on production wafers.
In fact, nearly all photomask layers at the 65nm process node will require some sort of RET — either optical proximity correction (OPC) or phase-shifting technology — and as a result, the complexity of mask synthesis is making it much harder to avoid printed errors on processed wafers due to the distortion of exposure light in subwavelength lithography.
"Theoretically, mask synthesis software and mask data preparation fracturing software, which is also becoming more complex, takes all this into account so that there won't be any problems," says Tom Kingsley, product marketing manager for lithography verification tools at Synopsys Inc. "In a perfect world you have perfect tools, but because of the complexity in those tools and the transformation of design layouts for RET masks, it now pays to add new verification steps into the flow."
To do that, Synopsys is driving its "silicon vs. layout" verification tool, called SiVL, into an emerging software segment, dubbed "virtual stepper systems," Kingsley says. "A virtual stepper system will look at the set image from a mask design. It will simulate how it prints on the wafer and make an intelligent determination of whether or not 'defects' on the masks will result in real defects [on the wafer]," he adds. "With masks now costing up to $100,000 for a poly layer and over $1 million for an entire mask set, the need to verify is becoming important."
In May, the Mountain View, CA-based design automation supplier rolled out a greatly enhanced version of SiVL, which became a Synopsys product after the company acquired Numerical Technologies Inc. in 2003. The enhanced SiVL tool merges the original NumeriTech software with additional OPC modeling, mask synthesis, and new "intelligent" simulation capability that was being developed by Avanti Corp. prior to its acquisition by Synopsys in 2002.
The merged software tool adds scalable distributed processing performance for parallel computing of models and simulation engines on hundreds of processors, when needed. A key addition to SiVL is what Synopsys calls a "critical feature check library," which contains models of errors typically found in RET masks. These cover contact overlay mismatches, CD variations in gate structures, and problems with printed lines — such as unwanted pullbacks, extensions, pinches, or bridges, which can result from the interaction of exposure light from RET elements on subwavelength reticles. "If the characteristics of optics, dose, focus and resist are such and these figures are a certain distance from each other, they can interact optically to cause them to merge together," explains Kingsley, pointing to the problem of pinches or bridges on silicon.
The system uses models that are created and calibrated through a series of simulations taking into account all aspects of the lithography process, including the mask writer, scanner model, optics, resist, and the aerial image.
"It regresses through an actual etched wafer," Kingsley says. Some users are opting to break the simulation kernel down into stages to separate out the effects, such as etch or resist. Test patterns are used to build the models, which can be completed within a couple of months once processes and tool sets have been qualified for production. "SiVL verification will typically take 12 to 24 hours for a given mask layer," he adds.
For Synopsys, the proof in "RET closure" performance was unwittingly demonstrated by a major DRAM maker, which had begun beta testing the enhanced SiVL tool on a new 0.11µm memory design. The software had identified several errors in the photomask design for the 512-megabit DRAM chip, including a bridging defect in a metal layer. The lithography team recommended halting mask and wafer production, but the production team decided to push ahead with fabrication, believing that the newly enhanced SiVL tool was still unproven. Post production testing revealed the errors as predicted (see figure).
"Some companies in cost-sensitive chips, such as FPGAs and memories, are looking at tightly integrating mask synthesis and SiVL verification into the design loop. They invest huge amounts in designing core cells and they want to run designs through mask synthesis software in tight iteration loops," Kingsley says. "They might do that hundreds of times before a mask is made." — J.R.L.
System-in-cube builds wireless body networks
A novel three-dimensional stacked assembly technique is being pursued by the IMEC research organization in Leuven, Belgium, to build 1cm3 "system-in-a-cube" (SiC) modules for sensor and computing nodes in wireless bioelectronics networks. IMEC has developed the 3D SiC to combine a low-power microcontroller, a 2.4GHz wireless transceiver, crystals and passives for radio functions, dipole antenna, and power source for body area networks, which could be used by the health industry to gather vital body information from patients remotely.
 Wireless 3D sensor network demonstration device. |
The technology will first be used to make a wearable wireless electroencephalogram (EEG) to monitor brain activity in a joint-development project between IMEC and the University Hospital Leuven. As part of IMEC's Human++ program, researchers are developing a range of concepts for sensor networks that communicate body information to a central intelligent node, which will transmit wireless data to base stations.
Separate computing, radio, sensing, and power-source functions are layered in the 3D SiC. Each layer connects to the neighboring layer using a dual row of fine-pitch solder balls. The stacking technique will allow a variety of 1cm3 modules to be built for body networks and other applications, according to IMEC. The bottom layer uses a standard ball-grid array footprint. An ultralow-power radio will be demonstrated using a prototype transmitter, based on 0.18µm RF-CMOS, in 1Q04. The first ultralow-power building blocks in 90nm RF-CMOS are planned in early 2005. — J.R.L.