Yield improvement by defect reduction in metal and via module cleans
09/01/2004
In wafer cleaning, a series of tradeoffs always exists — balancing chemical cost, process throughput, and removal efficiency vs. particle redeposition, wafer surface alteration, and potential etching of the exposed thin films.
Front-end-of-the-line (FEOL) cleans are less prone to robustness issues because sacrificial films are typically used during fabrication, allowing for the undercutting of particles throughout film removal. Open topography also allows intimate fluid contact with the surface in FEOL cleans. As wafers move into the back-end-of-the-line (BEOL), however, some features are recessed, such as contact and via holes, restricting cleaning chemistry access to the interior surface and limiting contaminate removal. BEOL etch-polymer characteristics also have varying properties due to feature density, exposed films, and etch chemistries.
AMI Semiconductor studied problems resulting from insufficient solvent cleaning of metal lines and via holes that can lead to killer particle defects. The work also focused on residual etch-polymer issues, which cause yield loss and reliability problems. Using sensitive electrical and optical inspection techniques, it was discovered how inappropriate BEOL cleans and process defects originating from cleaning tools themselves were limiting yield.
BEOL clean tradeoffs
A common tradeoff is cost vs. the robustness of cleaning steps. Hydroxylamine (HDA) based chemistries are known for their ability to remove polymers from interconnect hole and metal lines while having little or no impact on films undergoing cleaning. However, HDA chemistries have higher material and disposal costs and are environmentally hazardous.
 Figure 1. A partial W-filled via with void extending up the metal sidewall. |
Initial investigations of a weak acid solution for post-metal etch cleans showed promise. However, yield analysis of test lots showed periodic single-via failures. Electrical testing found the failures occurring in vias at the end of isolated metal lines. By isolating and cross-.sectioning the failing sites, a distinct new failure signature was found for partially filled tungsten-plug vias (Fig. 1). SEM and TEM showed two significant points: an empty voided area extending up the sidewall of the bottom metal line and along the antireflective coating (ARC) layer to the bottom corner of the via; and the presence of carbon in the void as measured by energy-dispersive x-ray analysis (EDX). These two observations indicated residual post-metal etch polymer eventually resulted in a partial W-plug fill.
To assist in anisotropic metal etching, etch polymer is continually grown and/or deposited and sputtered off the exposed wafer surfaces, including metal lines and photoresist patterning. Pattern inspection after etch indicates that there is more polymer on the surfaces that were orthogonal to the chemical ion etch plasma than those in line with the plasma stream. After etching, the photoresist and some etch polymer is removed using an oxygen plasma process. Some polymer remains after ash, due to polymer increase on the sidewall. Compounding the problem is an even higher amount of polymer seen on metal lines in areas where a large amount of metal was removed. This location may further tax the post-ash wet cleans; therefore, a marginal clean would be more likely to leave residual etch polymer on the isolated features, matching the failure location of the partial filled W-plug vias.
Investigation showed that polymer folds inward at the end of a metal line. Without complete metal etch-polymer removal, the etching of vias landing at the end of isolated metal lines is likely to expose residual metal etch polymer on the via sidewalls. The HDA chemistry used for the via clean would then remove any exposed metal etch polymer at the bottom of the via — thus creating the void seen extending along the top of the ARC layer and down the metal line. In the subsequent liner/barrier deposition step, a discontinuous film would be created.
Ti/TiN liner/barrier films are critical for proper via formation. The Ti layer reduces interfacial oxide impurities by reducing silicon oxide through the formation of TiO or TiO2, thereby improving adhesion and reducing resistance between the via plug and an interconnect line. The TiN layer is a protective "barrier" between the Ti and WF6 precursor, preventing the reaction of fluorine with titanium (i.e., preventing the formation of the well-documented W-volcano failure). The TiN layer is also used as a glue layer for adhesion and nucleation of CVD W [1]; hence, a break in the sidewall coverage does not allow the W to deposit in the bottom corners of the via. This results in "bread-loafing" that pinches off the via before W-deposition is completed. The current HDA-based chemistry must be kept to prevent this failure until a more robust alternative is found.
Inline scans reduce via failures
Occasionally, routine failure analysis of a yield monitor found die failures due to empty vias, where no metal was deposited. These failures occurred on all interconnect levels and often on one via in a region of many other "good" vias. A particle located over a via before liner/barrier deposition would explain the failures. Overlaying particle inspection maps and sorted die bit maps showed that a large percentage of the failures occurred where no particle was found by inline scans.
The first step was to increase scan sensitivities. Increasing the detection sensitivity on the KLA 2132 and Inspex Eagle inspection tools showed higher particle levels at each step in the via module. The most significant increase in particles occurred after the PVD liner/barrier deposition. Thorough statistical process control particle testing of the metal deposition tools could not explain the particle levels seen on product wafers. Therefore, it was believed that the liner/barrier deposition was highlighting incoming defects and allowing them to be seen by metrology tools for the first time after metal deposition.
Film thickness, number of metal layers processed, and pattern density combine to increase variation in background noise seen by inspection tools. As background noise increases, only large defects can be seen due to low signal-to-noise ratios generated by small defects. A single-level via short-loop monitor was created to minimize noise from underlying process layers. Stepwise scans of the new monitor found 0.5–1µm particles landing above the vias after the HDA via clean. Following some of these via clean defects through the metal module verified them as the cause for empty vias (Fig. 2).
 Figure 2. A post-via clean defect blocking liner/barrier deposition into the via. |
At AMIS, post-via etch cleaning is performed in a batch rotor spray tool with wafers rotating past fixed chemical-spray nozzles. Within the tool, a Teflon cassette holds wafers in the rotor chamber. EDX analysis of the particles causing empty vias showed a carbon-to-fluorine peak ratio roughly matching the ratio seen for a comparable EDX scan of the Teflon cassettes. A review of fluorocarbon defect locations showed approximately half landed directly above the via holes, potentially indicating some type of attractive forces between the fluorocarbon defects and the via holes, since the area fraction of via holes to dielectric surface on the wafer was small. It is speculated that solvation forces cause the lyophobic Teflon particle to minimize the surface area exposed to the liquid, attracting particles to the vias, and electrostatic forces between the particle and wafer increases particle retention.
Further investigation would provide an understanding for the disproportional hole vs. dielectric-surface collection ratio and possible ways to prevent
educe any Teflon particle collection by the wafer. Regardless of mechanism, the propensity for the fluorocarbon defects to land over the top of via holes significantly influences device fabrication.
Routine SPC testing of the solvent tool did not detect the 0.5–1µm fluorocarbon defects. In addition to surface condition differences, differences also exist in wafer edge profile between product and bare Si test wafers. The bare Si test wafer used for SPC testing has a relatively smooth edge. During the via cleans, the wafers spin within the cassette due to the rotation of the rotor. It is hypothesized that as the rough-edged wafer spins within the cassette, the wafer acts like a saw, wearing down the cassette and producing Teflon particles.
Additional tests using the highly sensitive via module short loop were performed to verify the hypothesis and further study the cassette/product-wafer interaction as the particle source. These tests showed that the age of the cassette had a significant impact on the number of fluorocarbon defects generated. It is assumed that the HDA chemistry softens/breaks down the Teflon cassette over time, making it more susceptible to the saw-like rotation of the wafer within the cassette. By increasing cassette change-outs, a significant reduction in empty-via generating particles has been achieved.
Conclusion
BEOL cleans require a robust cleaning solution and process to handle variations in residual etch polymers seen on metal lines. During the investigation of a weak acid chemistry for post-metal etch cleans, a new failure mechanism of partial W-filled vias was found. The failure was traced to insufficient metal etch-polymer removal that resulted in polymer curling over the end of the metal line. After via etching and cleaning, the metal etch polymer was removed from the via corners, making a void where the liner/barrier could not be deposited. The noncontinuous liner/barrier film then prevented sufficient W-fill of the via.
BEOL cleans also must maintain very low defectivity levels to prevent yield loss. Failure analysis of a yield monitor showed die loss due to empty vias. A short-loop monitor was created to improve detection sensitivity, and showed metal deposition into the via being blocked by fluorocarbon particles. A series of tool tests showed the product wafer rotation in the spray solvent tool's cassette was the source of the fluorocarbon defects. Routine cassette change-outs have dramatically reduced empty-via failures and have shown the need for particle-neutral BEOL cleans.
Acknowledgments
The authors would like to acknowledge Keith Ross, Madalena Overocker, Phil Sherbenou, Deb Florence, Todd Corsetti, and the entire failure analysis and wafer inspection teams. Teflon is a registered trademark of DuPont.
Reference
- R.A. Powell, S. Rossnagel, PVD for Microelectronics: Sputter Deposition Applied to Semiconductor Manufacturing," California: Academic Press.
Cory Hatcher is a process engineer at AMI Semiconductor Inc., 2300 Buckskin Rd., Pocatello, ID 83201; ph 208/234-6314, fax 208/234-6740, e-mail [email protected].