Optical interconnects promised by III-V on-silicon integration
08/01/2004
The 2003 International Technology Roadmap for Semiconductors (ITRS) notes that monolithically integrated, low-cost light emitters, detectors, and modulators are interesting possible solutions for impending silicon CMOS interconnect challenges. Although Si-based light generation, absorption, and modulation technologies have been explored extensively, their usefulness has been largely limited due to the indirect band gap of Si. III-V compounds, on the other hand, have robust photonic properties that can be tailored for operation at various wavelengths, with fast light-conversion speeds and sufficient light-power output for many photonic applications.
Overcoming defect challenges
The merger of the photonic properties of III-V compound materials with the ease of integration and scalability of Si microelectronics would enable many avenues for optoelectronic communication at various levels of the interconnection hierarchy. However, III-V compound-on-Si integration schemes pose several implementation challenges; three major types of defects that must be addressed as part of a III-V compound-on-Si integration scheme are shown in Fig. 1.
 Figure 1. Defects in III-V compound-on-Si integration schemes. Originally, a threading dislocation emanates from the SixGe1-x film(s). |
The difference in lattice parameter — i.e., the lattice mismatch — between III-V compounds and Si has been the primary integration challenge (Fig. 2). Gallium arsenide (GaAs) and indium phosphide (InP) are lattice-mismatched to Si by 3.9% and 7.5%, respectively. Direct epitaxy of GaAs or InP on Si leads to the evolution of extremely large stresses at the lattice-mismatched interface, which typically results in a nonplanar growth mode and nucleation of dense networks of threading dislocations. Typically, the resulting threading-dislocation density (TDD) is on the order of 1010/cm2, which is much higher than the residual TDD (~103/cm2) found in bulk GaAs and InP wafers.
For a typical laser diode or detector geometry that might encompass a total device area of 1000µm2 on bulk III-V compound substrates, one device in a hundred (i.e., 0.01 threading dislocations/.device) would contain a threading dislocation. A typical device fabricated on III-V compound materials directly deposited on Si would contain 10,000 dislocations. Threading dislocations are known to act as nonradiative recombination centers in photonic devices, thereby reducing minority carrier lifetime and optoelectronic conversion efficiency. Nonradiative recombination at a threading dislocation can also promote defect reactions that facilitate the formation of dark line defects (DLD) in lasers, which can ultimately lead to catastrophic laser failure. Direct epitaxy of III-V compound materials on Si is generally considered unsuitable for photonic device needs, so attention has been placed on intermediate or buffer layers to minimize threading dislocation nucleation.
To accommodate the lattice mismatch between Si and GaAs, compositionally graded silicon-germanium (Si1-xGex) alloys have been implemented to engineer a lattice constant to that of Ge, which is very closely lattice-matched (only a 0.1% mismatch) to GaAs, while achieving a TDD as low as 106/cm2. Although the TDD is still higher than that inherent to bulk Ge or GaAs substrates, it has been demonstrated that it is low enough to significantly improve the minority carrier lifetimes [1] and provide GaAs-on-Si material quality sufficient for preliminary device investigations. Projections indicate that further optimization of the TDD to the 104/cm2 range would provide minority-carrier lifetime performance indistinguishable from bulk compound semiconductor substrates.
For the case of InP integration with Si, the SixGe1-x layer could potentially serve as the first bridge in lattice constant to that of GaAs, and from there on, compositionally graded indium gallium arsenide (In1-xGaxAs) or indium gallium phosphide (In1-xGaxP) alloys could be implemented to engineer the lattice constant to that of InP. Although compositional grading has been implemented for various materials systems for many years, the understanding of dislocation nucleation and propagation processes for these materials systems is not complete; further investigation will be required to reduce dislocation density to the sub-104/cm2 regime.
While dislocation introduction during lattice-mismatched epitaxy is by far the greatest barrier to integrating III-V compound materials with Si, there are several other challenges. III-V compound materials are composed of two different atomic sublattices. During epitaxy on a group IV substrate (e.g., Si or Ge), domains with sublattice shifts may nucleate; where two different domains merge, sheets of wrong nearest neighbor bonds, antiphase boundaries (APB), can occur. These APBs are planar defects acting as nonradiative recombination centers that debilitate device performance. With proper epitaxial initiation sequences, they can be averted.
Another integration problem that must be accounted for is management of thermal expansion mismatch stresses, which can lead to crack formation in the III-V compound layers. Strategies to avoid this include the use of layer transfer techniques to minimize total film thickness and thermal mismatch stresses.
Results after defect mitigation
With the effects of defects properly mitigated, recent demonstrations of GaAs-based lasers on Si have shown promising results [2]. Groenert et al. first showed lasers integrated on Si had differential quantum efficiencies of 24% compared to identical devices on GaAs that displayed efficiencies of 32%. (Both sets of devices lacked facets with antireflection coatings, which lowered the overall efficiency values.) DLD-induced degradation limited the lifetimes of these devices to ~15 min. After incorporation of an optimized contact geometry to reduce series resistance and planarization of the Ge-on-Si substrate to reduce surface roughness, second-generation devices displayed differential quantum efficiencies of 40%, as well as identical turn-on voltages and characteristic temperatures to the GaAs-based control devices. The devices also displayed room-temperature lifetimes >4 hr, an improvement of >1200%.
The final challenge that remains largely unaddressed is the optimal III-V device integration sequence with Si-compatible CMOS processing and the coexistence of CMOS circuitry. Although the required processing will introduce additional complexity, modern CMOS processing has already evolved with the introduction of copper interconnect metallization and Ge implantation, two materials well known for disrupting CMOS performance if not integrated properly.
Thus, the extension to III-V compounds is possible, but will require further innovation. More important, the proper vehicles for qualification of III-V compound-on-Si technology will have to be identified. It would be impractical to transition the technology to production-readiness as a generic optoelectronic platform that is devoid of better-defined application criteria.
References
- C.L. Andre, et al., Appl. Phys. Lett., Vol. 84, p. 3447, 2004.
- M.E. Groenert, et al., J. Vac. Sci. Technol. B 21, p. 1064, 2003.
For more information, contact Mayank Bulsara, co-founder and CTO of AmberWave Systems, 13 Garabedian Dr., Salem, NH 03079; ph 603/870-8700, fax 603/870-8608.