Issue



Exploiting design regularity foroptical RET lithography


08/01/2004







Semiconductor lithography is facing a critical crossroads. In the mid-1990s, minimum feature sizes began to drop below available exposure wavelengths and over the last several years this trend has continued. State-of-the-art microprocessors currently have minimum gate lengths in the 50–70nm range, imaged by lithography tools using 193 and 248nm wavelengths.

There have been unexpected delays in the development of 157nm exposure technology, and next-generation lithography methods are nowhere near manufacturability. Therefore, optical lithography using 193 and 248nm wavelengths will be forced to extend further into the subwavelength regime more than ever before.

Recently, there has been encouraging progress in immersion lithography that offers the potential to extend numerical apertures (NA) above 1.0, but there are polarization challenges for practical implementation of hyper-NA lithography methods.

Increasingly complex resolution-enhancement techniques (RETs) will be required, significantly driving up photomask and design costs. Yield is also expected to suffer in this regime. "Deep subwavelength" optical lithography is technically feasible, but the key challenges of rising mask and RET-compliant design costs threaten to slow the advance of Moore's law.

This is especially true in areas of low- to moderate-volume applications, such as ASICs, where such costs cannot be amortized. A significant drop in new ASIC designs is already occurring. Research into maskless lithography is attempting to address the problem of low volume, but manufacturable systems are still a long way off.

A fundamental change in design approach can address most of these challenges and enable progress in cost-effective deep subwavelength optical lithography. Current design permits arbitrary placement of critical features such as transistor gates and contact holes. In the subwavelength imaging regime, such practice leads to unacceptably small process latitudes with, for example, serious problems controlling feature size through pitch.

Aggressive RETs need to be added at this point, resulting in substantially increased mask complexity. Even then, some feature types and pitch values are considered "forbidden" in terms of printability and are not allowed in the design. Current design practice is compounding alarming increases in mask complexity and cost, as well as RET-compliant design difficulties and costs. This trend cannot be sustained.

Over the past several years, grid-based RET approaches have been explored [1–4], representing a fundamental design-paradigm shift. Arbitrary placement of critical features is no longer allowed in such methods. One particular example is the "dense-only template" approach, exemplified in the GRATEFUL [5] method (Gratings of Regular Arrays and Trim Exposures for ULSI Lithography).


Figure 1. Only simple phase-shift grating-template masks are in GRATEFUL. Different orientations are implemented in separate resist layers. This example requires four exposures. Restriction of gates to a single orientation reduces the requirement to three exposures, and the use of a graytoned trim mask reduces this to only two exposures. Similar methods can be used to image contact holes.
Click here to enlarge image

With this technique, all critical features are laid out on dense regular grids with customization performed by subsequent trim exposures (see Figs. 1 and 2). RET compliance of the design is ensured from the start by simply restricting critical features to allowed grids. Lithographic process latitudes are greatly enhanced, and lower k1 exposures can be practically imaged, owing to the regular nature of the critical feature images. Dense grating images have the largest process latitude in the low-k1 regime.


Figure 2. An experimental example shows the GRATEFUL method applied to transistor gate lithography. The complex gate pattern is formed from simple grating-template masks. Good CD control was achieved through pitch without the use of OPC features.
Click here to enlarge image

Since only dense critical features are imaged, there is little to no need for complex optical proximity correction (OPC) features, which simply mask fabrication requirements. The same dense template masks can be reused for many different designs, with different trim exposures, thereby amortizing high-end mask costs.

There are a number of key issues associated with the adoption of a grid-based design paradigm. First is the restriction of all critical features (i.e., gates and contact holes) to a permitted grid. The implications of such restrictions to circuit cell density form another important concern. Preliminary research suggests that a circuit density penalty does not necessarily result from the adoption of such a method [4, 5]. Proper choice of grid can result in circuit densities competitive with current design practice. The key here is that efficient design must take into consideration the grid restrictions. Conversion of legacy designs to a grid approach will likely result in a density penalty.

Grid-based designs will likely require multiple-exposure imaging, which implies added cost. The lithography community already accepts double-exposure complementary phase-shift methods, and there is discussion of double-dipole image decomposition for the future [6]. Preliminary cost analysis [7] suggests that multiple-exposure dense-only template lithography can be cost-effective over a wide range of wafers shot per photomask, covering many key application areas, especially ASICs (see Fig. 3).


Figure 3. Lithography cost analysis with 90nm node technology.
Click here to enlarge image

Grid-based designs also have an advantage in the hyper-NA (NA≥1.0) regime, which will occur if immersion lithography is adopted. In this regime, only TE polarization has high imaging contrast, implying polarization control of the illumination optics. Linear polarization is simplest to implement and has the highest RET performance, but requires geometries restricted to one orientation, implying multiple exposure decomposition. Grid-based designs fundamentally restrict critical features to regular grids, thus making the layout compatible with linearly polarized illumination from the start.

Another possible grid-based RET method involves double exposure of the same mask to print critical features with enhanced process latitudes. For example, a 2D checkerboard phase-shift mask can be exposed to two orthogonal dipole illumination exposures without changing the mask. This gives a contact array pattern with double the image contrast compared to a single exposure [8]. Similar methods are possible to enhance polarization contrast in the hyper-NA regime.

It looks like optical lithography is here to stay, at least for the next decade. The fundamental change in design paradigm offered by grid-restricted methods can enable the practical, cost-effective extension of currently available exposure tools into the deep subwavelength feature-size regime. Such methods are also compatible with the polarized illumination required in hyper-NA lithography.

References

  1. A. Suzuki, K. Saitoh, M. Yoshii, SPIE, Vol. 3679, pp. 396–407, 1999.
  2. M.D. Levenson, J.S. Petersen, D. Gerold, C. Mack, SPIE, Vol. 4186, pp. 395–403, 2000.
  3. M. Fritze, B. Tyrrell, D.K. Astolfi, D. Yost, P. Davis, et al., SPIE, Vol. 4346, pp. 191–204, 2001.
  4. J. Wang, A.K. Wong, SPIE, Vol. 5043, pp. 134–141, 2003.
  5. B. Tyrrell, M. Fritze, D. Astolfi, R. Mallen, B. Wheeler, et al., J. Microlith., Microfab., Microsyst. (JM3), Vol. 1, No. 3, pp. 243–252, 2002.
  6. A. Torres, F.M. Schellenberg, O. Toublan, SPIE, Vol. 4691, pp. 407–417, 2002.
  7. M. Fritze, B. Tyrrell, R. Mallen, B. Wheeler, SPIE, Vol. 5042, pp. 15–29, 2003.
  8. M. Fritze, B. Tyrrell, R. Mallen, B. Wheeler, P. Rhyins, et al., JVST B, Vol. 20(6), pp. 2589–2596, 2002.

For more information, contact Michael Fritze at MIT Lincoln Laboratory, 244 Wood St., Lexington, MA 02420; ph 978/781-2626, [email protected].