Topography control using sacrificial capping layers
08/01/2004
Capping layers can protect porous low-k materials from subsequent processes. Although the introduction of porous low-k dielectrics has been pushed out, there are good reasons to use capping layers now. This article focuses on the impact of using sacrificial cap layers on the copper-barrier CMP process and on CMP consumables selection. Among the CMP-specific benefits of using sacrificial caps are better topography control, process stability, and throughput.
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The use and selection of hardmask and capping materials for low-k integration have not yet been standardized within the semiconductor industry. Every company has its unique approach and reasons why its solution best fits a process; however, the benefits of a sacrificial layer from a purely CMP perspective can be evaluated regardless of the chosen solution.
Low-k dielectric materials are often capped with materials such as SiC, SiCN, SiO2, SiCOH, and Si3N4 to solve several possible complications in processing and reliability. When material is used to improve etch profiles or reduce plasma damage, this layer is referred to as a hardmask. If the primary function is to improve adhesion to subsequent layers, promote cleaning, protect the dielectric, or enhance the CMP process, it is called a cap (see Fig. 1a on p. 34). In the case of porous materials on which a conformal dielectric layer is applied after etch and prior to barrier, it is called a seal. The selection of each is driven by different considerations, and often one layer can serve multiple purposes [1]. If chosen and optimized with CMP in mind, these capping structures can produce robust processing solutions.
Ideal vs. reality in copper removal
Sacrificial capping structures used in conjunction with specific types of CMP processes allow for the less-than-ideal situations associated with real-world requirements such as throughput, design rule flexibility, and robust process windows. Copper CMP consists of two process steps: copper removal, clearing to the barrier; and barrier removal, which can include removing cap and dielectric layers. The ideal picture of copper CMP has a planar surface of copper being removed uniformly, arriving at the barrier layer simultaneously across the entire wafer (Fig. 1b). The reality is that nonuniformity, stacking topography from lower levels, and pattern dependence (Fig. 1c) require significant overpolish to avoid residual copper "puddles" and electrical short circuits (Fig. 1d). Overpolishing results in copper dishing, which must be as great as the underlying topography of the dielectric (Fig. 1e) [2]. A modest amount of copper-feature dishing is a necessary condition for consistent clearing, which in turn defines some of the requirements for the barrier-clearing step.
High-selectivity barrier removal process trap
The imperfections of CMP must be addressed when matching a barrier-removal CMP process to the expected range of incoming wafers from copper removal and the variation in underlying layers. An early pitfall for copper CMP prior to capping layers was using ultralow dishing copper-clearing slurry followed by a high-selectivity barrier slurry.
High-selectivity slurries combine a high barrier rate with low dielectric and copper rates. In a high-selectivity process, the barrier material is removed with minimal change in the copper and dielectric features; thus, the topography is the same as the dielectric deposition plus any remaining dishing of the copper. This is the "start flat and keep it flat" approach. On a metal level-one test wafer, the resistance distribution can be close to ideal, as the metal thickness will be determined by the well-controlled dielectric deposition thickness. In a multilevel wafer, however, the topography from each underlying layer will transfer through the dielectric as the deposition is conformal to the underlying surface. Low spots in the dielectric will be indistinguishable from features and create residual puddles of copper.
Using the high-selectivity process approach gives up one of the main benefits of CMP: planarization, the ability to improve the overall topography of a wafer. For the high-selectivity process to yield well, the topography after barrier CMP must be less than the dishing and erosion coming out of the copper clearing to barrier step. This type of process has no way to recover from excess topography caused by CMP or other process nonuniformity; therefore, it is inherently less stable than a less selective approach that improves the topography.
Where to correct topography
For process stability, the CMP process should handle a broad range of incoming topography and improve it. To do this, a significant amount of either dielectric or cap material has to be removed to bring the copper level closer to the dielectric level. Without a cap layer, the reduction in step height depends on the planarization efficiency of the CMP consumables. An important measure of this is the rate of step-height reduction vs. material removed. Figure 2 shows the reduction of dishing vs. the field dielectric removed.
 Figure 2. A graph of dishing reduction with dielectric removal. Note the convergence of removal rates of copper and dielectric on a pattern wafer during barrier polish. |
The copper removal rate starts out low in the pattern regions and accelerates as the dielectric is removed. As the removal rates of the dielectric and copper approach each other, the dishing level reaches an equilibrium value. Typical barrier polish processes stop well before equilibrium, but how quickly the process reduces dishing will determine how sensitive the topography is to variations in the amount of material removed. A process that operates on the asymptotic tail of the total indicated range curve (measure of all components of topography) will be more stable than one that is on the steep portion. The sacrificial cap provides the material needed for the process to operate in the more stable region.
In the case of a sacrificial cap, the underlying low-k material can be used as a CMP stop layer to further accelerate planarization and reduce the total amount of material that needs to be removed. Having the low-k film as a CMP stop enables a high removal rate for the cap relative to the copper, which in turn allows very quick initial planarization. A low removal rate on the underlying low-k material, equal to the copper rate, results in less final dishing. The equilibrium topography for the capped system is controlled by the copper and low-k removal rates, not the cap removal rates. The benefit of using such a CMP process is a significantly tighter final copper thickness over a wide range of pattern densities. This can be easily seen when comparing the electrical test results (Fig. 3). Notice the minimal spread in the resistance distribution, even with 50% overpolish, when a stop layer is used compared to without a stop layer.
To clear or not to clear the cap?
There are clear benefits to using a cap material, but there is no consensus today whether it is better to stop within the cap vs. removing the cap entirely. There are advantages to CMP for both approaches. As observed in Fig. 4a, removing the cap allows the low-k film to act as a soft stop and accelerates the planarization, allowing the cap to be roughly as thin as the incoming dishing from the first step copper process, typically 400–600Å. Furthermore, higher throughput can be achieved because higher cap removal rates can be utilized without the dishing becoming overly sensitive to polish time or uniformity across the wafer.
If the underlying dielectric is susceptible to damage from exposure to CMP chemistry and potential mechanical damage, leaving some cap material is a useful approach (Fig. 4b). Leaving some cap material, particularly if the cap is SiO2, has the advantages of ease of cleaning and, quite often, backward compatibility in the processing of previous product generations. On the downside are tradeoffs in increased keff and the need for more careful endpoint detection to avoid breaking through the cap and exposing dielectric.
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A compelling reason to leave some cap material in place is that the time-dependent dielectric breakdown has been reduced, in one case by an order-of-magnitude, when the cap was removed [3]. In that particular case, the integration scheme was a TEOS-capped CDO structure; a possible explanation is diffusion of ions from the process into the dielectric film but not into the cap material. One potential source of metals is the barrier slurry. To test this hypothesis, TEOS and CDO wafers, unpolished and polished with developmental barrier slurries from Rohm and Haas Electronic Materials, were measured using secondary-ion mass spectrometry (SIMS). The data in the table show that this slurry imparts no significant additional ionic content in the top layer of the material. No measurements of Ca and Fe were taken on the CDO, since SiC interferes with their detection. It is well known from silicon wafer manufacturing that slurries can be a source of ionic contamination; however, the results show that it is possible to make slurry that does not contaminate the exposed low-k material.
Conclusion
The realities of CMP require a nonselective approach to barrier polish for process stability and robustness over a range of patterns, and the recognition that significant dielectric material will need to be removed. Removing a sacrificial cap makes the CMP step tolerant of overpolish for copper clearing and dishing compared to a high-selectivity approach. The cap provides the material to do topography correction, and keeps the stacking tolerances from getting out of control at higher levels.
Utilizing a cap material, stopping before or on the underlying low-k dielectric, tightens the electrical resistance distribution. Contamination of the underlying low-k material can reduce interconnect reliability, but can be avoided by careful selection of CMP slurries. The decision to use a cap structure will be driven by overall integration and process concerns, but from a CMP process perspective, a capped structure has significant benefits. A more robust CMP process will translate into better consistency to downstream processes, and ultimately, higher electrical yields.
Acknowledgments
The author would like to thank Drs. John Quanci and Zhendong Liu of Rohm and Haas Electronic Materials and a Japanese device maker for their assistance in this work.
References
- F. Fusalba, "Advanced ULK Dielectric Materials for Sub 65nm Node within 300mm Interconnect Process," IITC 2003 Short Course.
- R. Barker, "300mm Cu CMP Process Development on a Single Platen for 65nm Technology," CMP-MIC 2004.
- Y. Yamada, "Copper CMP Process for High Reliable Copper Damascene Interconnects," CMP-MIC 2004.
Richard Baker received his PhD in mechanical engineering, and since 1996 has been with Rohm and Haas Electronic Materials CMP Technologies, 451 Bellevue Rd., Newark, DE 19713-9960; ph 302/366-0500.