Optimized illumination settings extend ArF lithography to 65nm
08/01/2004
The extension of 193nm ArF lithography to 65nm processes will be necessary because of delays and problems with 157nm tool deployment. Resolution-enhancement techniques such as darkfield alternating phase-shift masks, double dipole exposures, and chromeless lithography will be needed to apply ArF tools to the 65nm node while device makers wait for production-class high-NA immersion scanners to arrive around 2007. Optimum illumination settings have been recorded for poly-gate patterning of 65nm ICs with minimum gate pitches of 160nm using ArF tools that have 0.75NA and low partial-coherence optics.
The IC industry continuously pushes optical exposure technology to its limits. For example, 248nm krypton fluoride (KrF) lithography was extended to achieve subquarter-micron generation patterning in production. According to the 2003 International Technology Roadmap for Semiconductors (ITRS), 193nm lithography is still the industry's primary light source with mature lens designs and photoresist chemistry for potential use in 65nm and even 45nm generations [1].
Extensions of 193nm lithography gained momentum after 157nm-wavelength tools began to hit a series of barriers, including birefringence of lens materials, low transmission of pellicle materials, and resist chemistry that is too absorbent. Immersion lithography, based on 193nm argon-fluoride (ArF) light sources, has now gained favor because of its improved resolution capability [2].
While the industry waits for high numerical-aperture (NA) immersion tools to become production-ready, extensions of dry ArF lithography with resolution-enhancement techniques (RET) must be considered for 65nm process nodes and beyond. This article describes successful poly-gate patterning with a minimum pitch of 160nm using high NA and small partial coherence of ArF lithography in conjunction with darkfield alternating phase-shift masks (alt-PSM). It is possible to achieve through-pitch common process windows for gates with 65nm after-development-inspection (ADI) critical dimension (CD) at minimum pitch of 160nm. These ArF lithography settings deliver >0.30µm depth-of-focus (DOF), which can be used for 65nm-node production.
Research shows through-pitch proximity can be compensated for by optical proximity correction (OPC). It has also been determined that line-edge roughness (LER) can be improved a little by darkfield PSM techniques. However, LER was found to have a strong dependency on aerial image contrast. Shifter width was selected to obtain the largest process windows and minimize phase conflicts. To address the limits of PSM resolution, high-NA 193nm or liquid immersion lithography appear to be necessary for gate-pitch below 160nm.
 Figure 1. Definitions of alt-PSM layout features. |
Previously, UMC researchers successfully demonstrated the extension of 248nm lithography to 50nm gate patterning with alt-PSMs [3]. These results confirmed the simulation prediction that showed an optimal combination of shifter-width bias with undercut could be used effectively to correct the image-intensity imbalance [4].
Problems in manufacturing alt-PSMs have been solved, including three essential factors: overlay of second writing, the profile of quartz dry etching, and depth control [5]. UMC researchers have taken this work further to explore the extension of 193nm lithography with alt-PSMs for gate patterning and minimum pitch required for design rules in the 65nm node.
Issues with alt-PSMs
Several criteria should be met for successful use of alt-PSM technology. These include high aerial-image contrast; large usable depth-of-focus (UDOF); optimized mask error-effect factor (MEEF); and proximity — less design-rule constraint, less alt-PSM OPC difficulty, and less maskmaking difficulty. Key process tuning parameters to determine the process windows and those criteria of alt-PSMs are NA and partial coherence (sigma) of the illumination tools, as well as Cr regulator width and shifter width on the alt-PSM (see Table 1). The definitions of regulator width and shifter width are shown in Fig. 1.
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High aerial-image contrast of alt-PSMs will result from high NA and low partial coherence of the illumination tools, accompanied by small Cr regulator CD and shifter width. Optimum NA and sigma will result in the largest UDOF. This will also result in optimized MEEF and proximity through features with all the pitches. There are conflicts between these criteria, however — e.g., shifter width to UDOF and design constraints. For larger UDOF, a larger shifter width should be applied, but larger shifter width will produce many more phase conflicts and result in design-rule constraints.
In order to adjust the performance of alt-PSMs and satisfy all the criteria, optimization among these key process parameters is necessary. NA, sigma, and Cr regulator CD are first considered with the aid of simulation to maintain the through-pitch DOF >0.3µm for 65nm processes. Minimum shifter width is the next parameter to be determined to keep isolated features with enough DOF while minimizing the through-pitch proximity and MEEF.
Optimizing NA and partial coherence
Highest aerial-image contrast of 160nm-pitch alt-PSM features can be found at higher NA and lower partial-coherence settings. With the constraint of the smallest partial-coherence setting around 0.2 for most commercial 193nm scanners, the highest image contrast can be found around 0.75NA in the matrix splits of NA and partial coherence (Fig. 2). Aerial image contrast increases as the partial coherence decreases at a fixed NA. Acceptable high aerial-image contrast can be found at a lower NA setting, such as 0.65, if partial coherence could be reduced to 0.125 and below. However, no such low partial-coherence illumination systems are available as commercial production tools. This indicates that low NA settings — such as NA <0.7 — are not suitable for 65nm-generation pattern printing. On the other hand, aerial image contrast grows as the NA increases at a fixed partial-coherence value, and reaches a maximum point at optimum NA from 0.7–0.82. This explains why high-NA tools are expected to be widely adopted for the 65nm generation and beyond.
 Figure 2. Image contrast simulation of NA and partial coherence of 160nm pitch. |
As the Cr regulator width is set at 80nm, the difference between conditions of 0.75NA and 0.85NA can be distinguished in terms of through-pitch aerial-image contrast. Figure 3 shows the NA-dependent aerial-image contrast through-pitches from 120nm to 300nm with Cr regulator width set at 80nm and shifter width varies as pitches increase at the best focus (0). This indicates that 0.85NA can only have higher aerial images in the range of pitches <160nm. There is almost no difference between 0.75NA and 0.85NA at 160nm pitch and higher.
 Figure 3. Image contrast simulation of through-pitch by different NA (Cr regulator is 80nm). |
Aerial image contrast goes down gradually from 300nm pitch to 160nm pitch, and rolls off after 160nm pitch in the case of 0.75NA. The turning point of the roll-off for 0.85NA is then extended to ~140nm pitch, which also implies that the optical resolution limit for 0.85NA illumination conditions could be extended around 140nm pitch. This assumes an aerial-image contrast threshold at 0.5. Beyond 140nm pitch, higher-NA or immersion illumination tools are expected to overcome the resolution limitation and obtain large enough process windows.
 Figure 4. Image contrast simulation of focus difference using 0.75NA illumination setting (Cr regulator is 80nm). |
With illumination condition 0.75NA and low partial coherence, an alt-PSM with an 80nm Cr regulator can deliver a process window with 0.3µm DOF, considering only aerial image contrast at the minimum poly-gate pitch of 160nm in Fig. 4. This assumes the same behavior for positive and negative defocus conditions, and that the aerial-image contrast threshold is 0.5. As focus condition drifts from the best focus (0), the aerial image contrast decreases rapidly, especially around the limitation of 160nm pitch for the illumination condition 0.75NA. The results show a through-pitch common process window can be as large as 0.4µm DOF, if the minimum poly-gate pitch can be set at 180nm.
Shift and Cr regulator width optimization
Shifter width is one important factor in determining whether a circuit layout will be compliant to alt-PSM techniques. Shifter-width dependent Bossung curves are shown in Fig. 5. Simulation results of shifter widths from 200nm to 300nm show process windows generally increasing according to larger shifter width. The largest process window is found with a shifter width of 300nm. Cr regulator widths vary for the cases of different shifter widths to fit the CD targets at 70nm. As shifter width increases, the chance of phase conflicts also will increase because of limited space between critical gate features. Therefore, optimization of shifter width should be a compromise between process windows and phase conflicts. Isofocal CD behavior can be observed with a shifter width of 280nm, which may result in better CD uniformity.
 Figure 5. IDOF of isolated line simulation by a shift-width split. |
Shifter width of 250nm is the minimum value acceptable with considerations of phase conflicts and process window, in the case of 160nm poly-gate minimum pitch and 0.75NA illumination conditions.
Performance and resolution limits
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With a 0.75NA 193nm scanner and vinyl ether-maleic anhydride (VEMA) type photoresist process [8], the resolution limit can reach ~150nm minimum pitch, which matches the prediction of aerial-image contrast simulation. SEM images of photoresist profiles show little striation, which may be caused by low aerial-image contrast while using 193nm illumination.
Table 2 shows the Cr-regulator width dependence on CD and MEEF values. (The correct regulator width could not be shown before OPC because the CD increment on the test reticle was 5 nm.) The high MEEF value at 160nm pitch shows the resolution limit of 0.75NA 193nm lithography to be ~160nm pitch, which backs up top-down SEM images of resist profiles and simulation results.
 Figure 6. SEM photo of 140nm pitch for 60nm ADI-CD produced by alt-PSM of ArF lithography. |
Linearity of 0.75NA 193nm lithography can reach 140nm pitch. The top-down CD-SEM profiles of 140nm are illustrated in Fig. 6. However, the poor pattern striation is caused by poor image contrast. No process window margin for 140nm is observed under 0.75NA for 193nm lithography. Higher NA (at least 0.85) is necessary to resolve a 140nm pitch with 193nm alt-PSMs, as previously described.
LER comparison
In comparisons of ADI LER performance, alt-PSMs generally demonstrate 2nm less LER than binary masks. Alt-PSM LER could be controlled to 6nm or below through pitches in the comparison. Even for 160nm-pitch features, current 0.75NA process conditions can still resolve the tight pitch patterns, but the LER shows that contrast is not enough with the 0.75NA illumination condition and photoresist.
Poor aerial-image contrast is a major cause for larger MEEF and LER at 160nm pitch. To improve the image contrast, a 0.85NA or higher 193nm scanner and improved photoresist processes should address limitations in alt-PSM resolution, bringing it down to 140nm with reasonable process windows.
Summary
Alternating PSMs with 0.75NA ArF lithography and a suitable low partial-coherence setting can achieve a minimum poly-gate pitch of 160nm with large enough DOF to enable 193nm exposure tools to address processes at the 65nm node and beyond. It also appears that 0.85NA 193nm lithography, with suitable low partial-coherence settings, will push the minimum poly-gate pitch down to 140nm. For further poly-gate pitch shrinkage, higher-NA or immersion tools will be needed for 193nm lithography.
Optimization of Cr regulator and shifter widths is crucial for alt-PSM process tuning and windows. Cr regulator width is also an important parameter in adjusting printing CD targets. For 160nm minimum poly-gate pitch, a through-pitch common process window can be obtained at 0.3µm DOF with 0.75NA and low partial coherence, which is good enough for 65nm generation mass production.
References
- International Technology Roadmap for Semiconductors, 2003 edition, http://public.itrs.net.
- S. Owa, et al., "Immersion Lithography; Its Potential Performance and Issues," Proc. SPIE, Vol. 5040, pp. 724–733, 2003.
- C.Y. Fang, et al., "Challenges of 50nm Gate Process in Alternating Phase Shifting Lithography," Proc. SPIE, Vol. 4690, p.44, 2001.
- H.L. Cho, et al., "Practical Approach for AAPSM Image Imbalance Correction for Sub-100 nm Lithography," Proc. SPIE, Vol. 5130, p. 778, 2003.
- B.S. Lin, et al., "Implementing AAPSM in 90-nm Product with Practical Image Imbalance Correction," Proc. SPIE, Vol. 5256, pp. 103–111, 2003.
- H.W. Kim, et al., "Implementation of the ArF Resists Based on VEMA for Sub-100-nm Device," Proc. SPIE, Vol. 4690, pp. 533–540, 2002.
Shu-Hao Hsu received his MS in chemical engineering from National Cheng-Kung U. in Taiwan, and is now a principal engineer of the nonvolatile memory dept., Central R&D Embedded Memories Division, at United Microelectronics Corp., Hsinchu, Taiwan; ph 886/3-578-2258 ext. 56453, e-mail [email protected].
Shu-Ping Fang received his BS in electrophysics from National Chiao-Tung U., and is a principal engineer of the lithography module at UMC's Fab 8C.
I.H. Huang received his MS in chemical engineering from National Tsing-Hua U., and is a section manager of the advanced lithography department in UMC's Central R&D Division.
Benjamin Szu-Min Lin received his PhD in materials science and engineering from National Tsing-Hua U., and is now a senior department manager of the advanced lithography department in UMC's Central R&D Division.
Kuei-Chun Hung received his MS in chemical engineering from National Taiwan U., and is the senior department manager of the lithography module at UMC's Fab 8C.