A nonpenetrating 4PP measures USJ sheet resistance
08/01/2004
A new method using elastic-material (EM) probes to form nonpenetrating contacts to the silicon surface to measure the four-point probe (4PP) sheet resistance of USJ source/drain structures is described. Sheet resistance measurements on USJ implanted p+/n structures with SIMS junction depths as shallow as 15nm have been observed, with values obtained by EM probe consistent with expectations.
Source/drain (S/D) engineering is an important area in existing and future device development. Critical device parameters such as on-state drive current (IDS,ON) are highly dependent on the S/D series resistance (RDS). It is therefore desirable to have S/D structures with low sheet resistances, which require structures with high carrier densities. At the same time, threshold voltage (VT) roll-off due to short channel effects (SCE) increases as the channel length is decreased [1], and these effects need to be minimized. This requires a rectangular overall device structure [2] with thin gate dielectric, S/D junction depths, and channel carrier profile. Highly abrupt, steep-gradient carrier density profiles are also necessary in order to reduce SCE via channel charge sharing [3].
Careful consideration of all of these device performance issues leads to the fact that the S/D carrier density profiles must be highly abrupt box-like profiles with a high peak carrier density and a shallow junction depth (Xj). As an example, S/D structures with activated dopant densities at or near solid solubility with Xj<20nm are under development for the 65nm technology node.
 Accurate sheet resistance measurements are made by Solid State Measurements' elastic material four-point probe, which uses four independent kinematically mounted probes. |
Producing these ultrashallow-junction (USJ) structures demands careful process design of the pre-amorphization implant, S/D implant, and the dopant implant anneal. The USJ depths and level of dopant activation depend heavily on processing [3]. A suitable method for characterizing these USJ structures is the 4PP sheet resistance (RS) technique [4]. The measured RS is highly sensitive to the activated carrier density and Xj. This is a highly accurate, absolute method that has been used successfully on structures with deeper junction depths and layer thicknesses.
Conventional 4PP RS measurements generally use four penetrating, scrubbing probes placed in contact with the top layer of the semiconductor wafer. It is necessary for conventional 4PP probes to penetrate through any existing native oxide that exists on the semiconductor surface to make good electrical contact to the top semiconductor layer. A common problem is that the conventional 4PP method penetrates through the USJ S/D structure into the semiconductor substrate. Under these circumstances, the RS of the underlying substrate is measured. This generally results in low RS values and all sensitivity to the top USJ layer is lost.
Conventional 4PP basics and theory
 Figure 1. Illustrations of an EM probe contact to the surface of a dielectric material. |
In a conventional 4PP, the probes are generally conditioned to be penetrating so that any top native oxide can be compromised and a good electrical contact can be made to the top surface of the semiconductor. This methodology works well for 4PP measurements on bulk or thicker layer structures. As shown in the results section, however, conventional 4PP measurements produce invalid data for the case of USJ structures. The probes are not kinematically mounted so that probe scrubbing occurs, resulting in damage to the semiconductor surface, which can also lead to changes in probe spacing, s, from measurement to measurement.
The credibility of 4PP measurements is usually established by measuring a NIST traceable reference standard to ensure accuracy of the probes, corrections, IV instrumentation, etc. During the measurement, some simple checks are made to ensure the quality of each measurement, including a current polarity reversal check, and a half tolerance current check. The reverse current test checks the V/I measured with equal but opposite polarity currents, and the half tolerance test checks the V/I at full and half current levels. These checks are valuable for detecting measurement errors due to surface- and probe-related effects.
EM probe description
A basic description of an EM probe metal-oxide semiconductor capacitor (MOSCAP) structure is shown in Fig. 1. The contact shown is formed by controlled elastic deformation of the probe. A highly repeatable, nondamaging, and nonpenetrating contact is formed. In the case of silicon, the contact is made on the surface of an existing native oxide. Conduction through the native oxide occurs by direct tunneling (DT).
The probes are made of a material with properties such that little or no metallic oxide forms on the probe, and the oxide that does form is conductive. These properties make the probe ideal for IV applications. Examples of EM probe IV measurements made on 10, 30, and 90Å oxides are shown in Fig. 2.
 Figure 2. EM probe IV curves measured on thin oxides with a type C probe (step delay = 1000 msec). |
The current that flows through the 10Å and 30Å oxides is due to DT. DT current is primarily dependent on oxide thickness and, to a lesser extent, on injection barrier height. The current flow in the 90Å oxide is due to indirect tunneling, or Fowler-Nordheim tunneling, and depends heavily on injection barrier height or work function of the probe material. The DT mechanism is essential for EM probe 4PP. All of the EM probes are mounted on a kinematic bearing system with controlled descent and ascent, ensuring that no probe scrubbing occurs. The EM probe contacts shown in Fig. 1 are formed by lowering the probe onto a semiconductor surface, or dielectric, and elastically deforming the probe material. The resultant contact diameter is typically 40–60µm and depends on the probe geometry and applied force. EM probe MOSCAPs formed in this manner have been used to measure IV and CV on oxides as thin as 0.7nm [5].
EM gate 4PP description and theory
The conventional 4PP measurement relied on penetrating probes to make good electrical contact to the doped semiconductor surface; however, using these techniques on sub-50nm USJ structures can produce erroneous results. The actual limit and amount of probe penetration depends on the probe design, conditioning, and load. Generally, loads of ~100gm are used. EM gate 4PP measurements overcome the problems associated with conventional 4PP systems by using the same nonpenetrating, nondamaging probes that measure ultrathin gate dielectrics (<1.0nm) [5]. Figure 3 is a close-up illustration depicting the major mechanical differences between the probes.
 Figure 3. Penetrating vs. nonpenetrating 4PP designs. |
From the substrate physics point of view, all of the formulae for calculating sheet resistance or resistivity are the same. There are some distinct differences in the equivalent circuit for the EM gate 4PP. Unlike the conventional 4PP system, where electrical contact is made via probe penetration and scrubbing, the EM gate 4PP setup relies upon DT transport through the thin native oxide present on a semiconductor surface. Current transport by DT is limited to the case where the oxide physical thickness is <~4.0nm — usually the case for native oxides. Additionally, an applied voltage of at least ~0.5V between the current carrying probes is required, which is also generally true for 4PP measurements.
DT currents are observed for oxide thicknesses of ≤4.0nm. In this mode, DT and soft breakdown occurs. These processes are nondamaging and reversible. With thicker oxides (>5.0nm), indirect tunneling and hard breakdown occur. Even though the post-hard breakdown current level can easily reach 1mA, implying a low resistance contact, hard breakdown processes are undesirable since they can locally damage both the probe and wafer site. The EM gate 4PP system operates in the DT mode, which means that the surface oxide should not be >4.0nm.
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The potential is measured with a Kelvin-type setup where the input impedance of the voltmeter is high (~1E14Ω). In principle, this means that no current loop exists between the voltage-sensing probes. The measured potential is confined to the region where the current flows, which is in the substrate; so considering voltage sensing, no tunneling is required through the surface oxide. Only for the two current-carrying probes are DT current flows necessary for the measurements. During normal operation, EM gate 4PP measurements are operated in the fixed-current mode. A current of 1mA typically is applied for USJ S/D structures. Leaky junctions will also be detected by this technique, which is an advantage over most noncontact methods.
Examples of EM probe 4PP RS
The results of EM probe and conventional 4PP RS measurements made on p+/n USJ S/D structures are shown in Table 1 for a 550°C anneal. The samples are from a matrix of anneals with and without amorphous implantation. The EM probe RS values for the amorphous wafers are lower, as expected, due to higher activation with solid-phase epitaxial annealing. The nonamorphous wafers have high RS values due to low activation and shallower electrical junctions. SIMS values for the chemical junction depth are also shown. The values obtained from the EM probe 4PP are consistent with expectations. Three-day repeatability was 0.2%. The total atomic or chemical profile for representative samples, obtained with SIMS, is given in Fig. 4.
 Figure 4. SIMS profiles for representative p+/n USJ samples from Epion Corp. |
Arsenic implanted USJ S/D (n+/p) structures were also evaluated with the EM probe 4PP. The junction depths determined from SIMS and SRP were about 300Å. The sheet resistance for these samples was measured with the EM probe 4PP and with the SRP variable probe-spacing method [6]. Standard 4PP measurements were also done (labeled "RS advanced"). This 4PP used a kinematically based 4PP designed to be nonscrubbing and less penetrating than standard 4PP systems. Standard 4PP was performed on the wafer's backside to measure the substrate. Results are summarized in Table 2. The conventional 4PP measurements yielded low sheet resistances due to probe penetration through the top USJ S/D structure. This occurred despite the kinematic mount. Three-day repeatability of the EM probe 4PP was 0.65%.
 Figure 5. Comparison between a 4PP, an EM probe 4PP, and a Hg 4PP. |
In addition to the two cases presented, comparisons have been made to another nonpenetrating 4PP design that uses mercury (Hg) probes. Hg contacts are nonpenetrating because they are formed with a liquid metal and use a pressure near atmosphere. The use of Hg may be undesirable for in-line or off-line tools in some wafer fabrication facilities.
 Figure 6. Critical Xj <30nm before 4PP probe penetration. |
A comparison between EM probes and Hg probes for S/D structures with junction depths ~120Å is given in Fig. 5, showing good agreement between both measurement methods. Backside RS was also measured for these samples. A comparison of RS ratio to junction depth by SIMS is shown in Fig. 6. For junctions <30nm, issues with standard 4PP begin to appear due to probe penetration.
Conclusion
A new, nonpenetrating, and noncontaminating method has been presented for measuring the sheet resistance of ultrashallow S/D structures. Elastic-material gate 4PP RS measurements were described; gate dielectrics as thin as 7Å were credibly measured with EM probe CV and IV. Because the technique is based on DT, EM probe 4PP measurements can be made on semiconductor wafers that have a native oxide present.
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Several cases were presented, including one for USJ p+/n, and one for n+/p USJ S/D structures. It was found that the EM probe 4PP could measure S/D structures with minimum junction depths of 150Å. Conventional 4PPs were found to be limited to about 300–400Å and deeper. The three-day repeatability of EM probe 4PP RS was found to be better than 1%.
Acknowledgments
The authors are grateful to Epion Corp. for providing the p+/n USJ samples; and to James Chen of Four Dimensions Inc. for the Hg four-point probe measurements.
References
- S. Wolf, The Submicron MOSFET, Vol. 3, Ch. 3, 1994.
- "Sixth International Workshop on Fabrication, Characterization and Modeling of Ultra-Shallow Doping Profiles in Semiconductors," 2001 USJ Conf. Short Course.
- "Sub-100nm CMOS," 2001 IEDM Conf. Short Course.
- D.K. Schroder, Semiconductor Material and Device Characterization, J. Wiley and Sons, 1998.
- R.J. Hillard, P.Y. Hung, W. Chism, C. Win Ye, W.H. Howland, et al., "Characterization and Metrology for ULSI Technology," Proc. AIP Conf. 683, p. 796, 2003.
- SSM SRP Seminar, 2002.
Robert J. Hillard is senior scientist at Solid State Measurements Inc., 110 Technology Dr., Pittsburgh, PA 15275; ph 412/787-0620, fax 412/787-0630, e-mail [email protected].
John Borland is the founder of J.O.B Technologies, 5 Farrington Ln., South Hamilton, MA 01982; ph 978/808-6271, fax 978/468-1187, e-mail [email protected].