Issue



How buffer layers can provide stress management for wafer-level chip-scale packages


08/01/2004







Wafer-level packaging (WLP) holds significant promise in enabling higher performance, smaller form factors, and cost savings in IC products, but the introduction of new materials in semiconductor manufacturing raises reliability considerations. Poor mechanical properties of low-k interlayer dielectrics raise the risk of damage to devices during packaging processes. New lead-free alloy soldering materials also require higher temperatures during the reflow process, increasing the potential for physical stress on ICs. This article discusses the need for stress buffer layers, their performance characteristics, and processing for WLP.

The physical stresses in WLP and related flip-chip packages depend upon a combination of several factors, such as device size, architecture, and operating conditions, as well as the actual package design and materials of construction. The use of traditional silicon-dioxide (SiO2) insulators as an interlayer dielectric (ILD) has not demonstrated any fundamental problems in the implementation of advanced packaging designs. However, the introduction of low-k materials (k<3.0) and future utilization of ultralow-k ILDs (k<2.8) have made a critical issue of the stress imposed on the device by the package.

Because of their poor mechanical properties, new low-k ILDs have shown susceptibility to delamination and cracking in packaging processes, such as backgrinding, dicing, wire bonding, and flip-chip bumping [1]. As physical properties degrade with increasing porosity, the packaging of ultralow-k ILDs is expected to become even more difficult.

Another factor in WLP is the industry's migration to lead-free alloy soldering materials used as the second-level interconnect. Most of the proposed lead-free materials have a high melting point and a high modulus of elasticity. Therefore, during the solder reflow process, significant stresses may be imposed on ICs. It has also been reported that the stress from a solder ball cooling during the bumping process can damage a device by separating the bond pad from the interlayer dielectric [2].

A solution is required to mitigate the stress that packaging will place on these leading-edge devices, which use low-k dielectrics and/or lead-free solders. One way to manage this stress is the application of a low-modulus stress buffer layer [3]. Based on actual thermal cycling data, a manufacturer estimated life between 1100 and 2572 cycles for 8×12mm and 9.6×15.2mm devices using a 300MPa stress buffer layer.

Another method for increasing reliability of a wafer-level (or flip-chip) bare die package is by increasing the stand-off height from the solder ball to the die, which can be modeled using the Coffin-Manson equation for predicting reliability [4]. Theoretically, one could lower the modulus and increase the thickness of the stress buffer layer to increase the reliability of the final packaged device.

Lithography process requirements

These thick-film stress buffer layers and other build-up layers for incorporating off-chip functionality must be processed in a manufacturing environment, not just a development laboratory. Proposed thick-film structures have been difficult to implement using current frontend wafer-processing equipment. While lithography requirements for advanced packaging are subject to the same production and yield demands as frontend semiconductor fabrication, the considerations for backend lithography are significantly different.

Thick-film lithography. The conditions necessary for successfully processing thick films differ considerably from their thinner counterparts. With thick films, the primary issues include aspect ratios, downstream plating performance, and process latitudes. In addition, ultrathick photoresists or dielectrics require a large exposure dose in order to achieve high aspect-ratio lithography. As such, there are advantages to using a 1× stepper with a broadband exposure system to maximize the illumination intensity at the wafer plane. A 1× stepper projects an aerial image that can be focused at various depths within a thick photoresist or dielectric film, making it capable of delivering steeper sidewall angles and higher overall image quality, regardless of the photoresist type or thickness. Contact and proximity aligners have essentially no focus capability, and their imaging performance is further degraded in thick-photoresist applications [5].

Process yields. Yield is typically a primary factor for any semiconductor process. By the time a wafer is ready for stress buffer layers, it has gone through numerous process sequences. Yield loss due to the lithography step has a direct and unacceptable effect on a manufacturer's bottom line. A combination of reworkable and nonreworkable yield defects introduced by contact and proximity aligners can lead to a significant increase in overall cost. Noncontact exposure techniques such as steppers can eliminate yield losses associated with contact and proximity aligners [6].

Low-modulus materials sometimes further compound lithography challenges for thick-resist materials. Even a slight contact by proximity or contact aligners can lead to significant rework considerations for lower-modulus materials, which are sometimes tacky after soft-bake. Therefore, projection optics with a large depth of focus provide the ideal solution for exposing these materials.

Silicon-based materials as stress buffers

The high transparency of new silicon-based formulations allows them to be patterned from much thicker films than dielectric materials that have traditionally been used as stress buffer layers. The materials can be spin-coated to 50µm or more in thickness and patterned with standard dosages of ultraviolet energy in one exposure. In order to achieve process flexibility for a range of feature heights, films as thin as 6µm have also been effectively created using these materials (see Fig. 1).


Figure 1. Film-thickness ranges for a) Dow Corning WL-5150, and b) WL-5350 and WL-5351 films.
Click here to enlarge image

Many other materials can be coated to a similar thickness, but usually do not have the transparency to be patterned efficiently. The transparency for photosensitive polyimides, for example, is dramatically reduced below 500nm, making the practical thickness for patterning typically 10–20µm, depending on the chemistry. In contrast, testing has shown that thicker films based on new silicon-based formulations maintain high transparency deep into the ultraviolet wavelength region. This covers the range of photolithography tool infrastructure currently in place and demonstrates excellent process flexibility. As a result, features can be easily patterned as 50µm-tall posts or 50µm-deep vias without multiple passes on the spin-coater. Transparency across the entire visible spectrum is shown in Fig. 2. The photosensitivity of the material is such that a wavelength of 365nm is typically required, but broadband or other ultraviolet energy that includes i-line exposure works equally well.


Figure 2. Transmission spectrum results of a 20µm film of Dow Corning WL-5350 photopatternable silicone. Transmittance at 300nm = 98.9%.
Click here to enlarge image

Another advantage of the new material set is high resolution, with the capability of achieving posts as small as 20µm in diameter in very fine-pitch patterns. These materials are compatible with many metallization schemes, allowing manufacturers to create fine-pitch metallized vias and posts with commonly used metal redistribution stacks of ≤30µm (see Fig. 3). The silicon-based formulations can be negative-tone patterned at reasonable aspect ratios with sloping sidewalls. Although Fig. 3 shows a 50µm via exposed at an energy level of 1050mJ/cm2, testing has shown that any exposure greater than 650mJ/cm2 has the same patterning capability. Potential applications include stress buffering, multilayer redistribution, and negative photoresists.


Figure 3. A 50µm via exposed at an energy level of 1050mJ/cm2.
Click here to enlarge image

These new materials can be hard-baked at any temperature from 150–250°C, whereas some materials currently used for redistribution layers require cure temperatures on the order of 300°C. In addition to reducing energy usage, the lower cure temperatures help minimize the effect of coefficient of thermal expansion mismatches between different materials within the device, such as the silicon substrate, the metallization stack, and the dielectric film.

The dielectric constant and dissipation factor of the materials also become key design issues. By delivering stable electrical properties at varying temperatures, these formulations contribute to higher signal integrity.

Reworking the stress buffer layer

In some applications, the ability to rework a partially processed wafer is an important consideration, whether from a need to recover an expensive substrate or a desire for flexibility. The level of difficulty depends on where in the process the rework step is required.

In general, processing of the wafer-level redistribution layers requires six steps:

  1. spin coat,
  2. soft-bake (solvent removal),
  3. UV exposure,
  4. post-exposure bake,
  5. development, and
  6. hard-bake.

With most conventional photodefinable materials, rework can be accomplished by using a solvent rinse after spin-coating. Many materials can be removed after soft-baking, but most cannot be easily reworked after further downstream steps. In contrast, the new silicon-based films can be completely removed before soft-baking in as little as five minutes with the help of a patent-pending stripping solution. These formulations differ from other materials, however, in that they can be fully stripped in about eight minutes — after lithography, post-exposure bake, and development. The solution is a nonacidic stripper that has been specially formulated to fully dissolve the patternable materials. Testing has shown no silicone residue remaining on the substrate surface after film removal and rinse.

Even after the hard-bake cycle, the cured film can be completely removed to salvage the substrate; cycle time will depend on the cure temperature used on the film. After a hard-bake at 180°C, for example, soak and removal time of a 20µm film would be about 40 min. Following a hard-bake at 250°C, the stripping and cleaning process generally requires about 90 min.

Summary

Advanced packaging methods are gaining industry acceptance. As flip-chip and WLP technologies continue to evolve, device manufacturers are faced with several material and processing challenges. Stress buffer-layer materials recently introduced to the market can be photopatterned as thick dielectric films and cured at low temperatures; they can even be reworked after the hard-bake process.

To address the processing issues associated with these relatively thick stress buffer layers, device manufacturers are applying traditional frontend lithography equipment to leading-edge backend packaging applications. Adoption of these techniques has been accelerated by the realization that imaging requirements for backend processing are subject to the same production demands as frontend semiconductor fabrication. The integration of new materials and processes for WLP has been validated in application trials, but future success is likely to depend on a close collaboration between materials and equipment suppliers, working with assembly and interconnect customers to develop practical solutions that can be implemented into an efficient manufacturing process.

Acknowledgments

Black Diamond is a trademark of Applied Materials Inc. SiLK is a trademark of Dow Chemical Co.

References

  1. J. Ling, et al., "Flip Chip Solder Bumping Compatibility on Cu/low-k Devices," presented at IMAPS Flip Chip Workshop, June 21–23, 2003.
  2. T. Goodman, "Extension of Wafer-Level Processing for Advanced Packaging," presented at APiA seminar at Semicon Japan, Dec. 4, 2003.
  3. "Post Passivation Lithography Analysis," commissioned study by E&G Technology Partners, September 2003.
  4. T. DiStefano, personal communication, June 18, 2001.
  5. W. Flack, et. al., "Characterization of an Ultra-Thick Positive Photoresist for Electroplating Applications," Proc. SPIE 2003, Vol. 5039, p. 1257.
  6. M. Ranjan, et al., "Productivity Enhancements in Advanced Packaging Lithography," Advanced Packaging, July 2003.

Michael Kunselman is the emerging devices marketing leader for packaging solutions at Dow Corning Electronics, 2200 West Salzburg Rd., Midland, MI 48686-0994; ph 989/496-6180, fax 989/496-6824, e-mail [email protected].

Lyndon Larson is a senior applications engineer at Dow Corning's Electronics Application Center.

James Alger is a technician focused on application development and film characterization of photolithographic materials.

Manish Ranjan is the strategic marketing manager at Ultratech Inc., 3050 Zanker Rd., San Jose, CA 95134, ph 408/325-6464, fax 408/577-3376, e-mail [email protected].

Scott Zafiropoulo is Ultratech's director of strategic marketing and marketing communications.