Issue



An analytical look at vertical transistor structures


08/01/2004







The combination of device enhancements, such as strained silicon configurations, SOI, and nonplanar transistor device structures, in conjunction with the current state-of-the art global efforts in high-k gate dielectrics, metal gate electrodes and elevated source/drain, offers a plethora of opportunities for IC manufacturers. Selecting the right option requires careful assessment. This article discusses several alternate vertical transistor structures that facilitate the continuation of Moore's law scaling [1], and it also discusses the implications of these structures for frontend characterization and metrology as per the 2003 edition of the International Technology Roadmap for Semiconductors (ITRS) (http://public.itrs.net).

Significant front-end-of-the-line scaling contributions have occurred in reducing the gate dielectric thickness, physical gate length, and extension junction depth [2] (Fig. 1) [3]. These scaling advances [1] have resulted in lower power dissipation/function, increased speed (intrinsic transistor gate delay), and increased transistor and function density [4–6].


Figure 1. Simplified cross-section of a high-k gate dielectric stack with accompanying physical gate length (Lg) and junction structures. Modified version of drawing in [3].
Click here to enlarge image

Potential solutions and approaches for scaling have been addressed by both material and process advances. These include arenas such as high-k gate dielectrics [7–12] and characterization of the interfaces involving the high-k gate dielectric, as well as the metal gate electrodes. In particular, interactions of the high-k with either the silicon [13] or the polysilicon gate electrode [14] — including interactions of the high-k material with both the silicon substrate and the polysilicon gate electrode [15] and charge instabilities associated with the high-k gate dielectric and/or its method of fabrication [16] — have also been considered. Poly-SiGe gate electrodes [17] and dual work-function metal gate electrodes with differing work functions [18] or a single, tunable work-function metal for CMOS optimization [19, 20] reduce the poly depletion effect [21] and boron penetration in pMOSFETs [21]. Metal gate electrodes also avoid reactions between the polysilicon and the high-k gate dielectric.

During the last few years, however, alternative nonclassical device structural configurations have received extensive assessment to maintain Moore's law [1, 22]. MOS transistor scaling of the physical gate length (Lg) to the sub-20nm regime has been observed to exhibit short channel effects (SCE) [21, 23, 24]. In conjunction with alternative CMOS device structures (i.e., vertical gate approaches such as the FinFET [25, 26] and other multiple gate configurations [27]), the opportunity for mainstream utilization of SOI has significantly broadened [28–34] in the drive to the "ultimate" CMOS device configuration [35, 36]. In that regard, the importance of characterization, metrology, and the associated precision-to-tolerance ratio (P/T) analysis cannot be underestimated.

Transistor scaling issues

The increased difficulty in meeting the required device metrics over the next 15 years certainly appears daunting [11]. These device parameters include the maximum saturated drain current Idsat; off-current Ioff; intrinsic transistor gate delay (CV/I), switching energy (CV2), and their dependence upon Lg; supply voltage (V); and equivalent oxide thickness (EOT). Although the challenges are substantial, they appear soluble with currently understood physical principles [4–6, 21]. Similarly, the exponentially increasing limits to scaling — such as increased subthreshold leakage, increased gate dielectric leakage, increased transistor parameter variability, and interconnect density and performance — appear to be comprehended [21]. Accordingly, silicon MOSFETs may be expected to scale in an essentially predictable manner from the present state-of-the-art 90nm technology generation (MPU Lg of 45nm) to the 22nm technology generation (MPU Lg of 9nm) [23, 24, 37], with band-to-band tunneling considered as the limiter at an Lg≈5nm. Recent advances towards the extreme scaling limit for Lg have been described for an electrically variable shallow junction MOSFET [37] and ultrathin Si channel MOSFETs [38].

Nevertheless, substantial issues that must be assessed involve control of SCE, impact of quantum effects in the bulk silicon (and polysilicon, an especially intricate topic, for the case wherein a polysilicon gate is still utilized). Additional critical issues include dopant stochastic variations (number and spatial location in channel) and other device/process fluctuation phenomena [39, 40], usefulness for enhanced mobility (beyond the universal mobility curve), impact of high substrate doping, control of series source/drain resistance, and related contact issues. Two significant initiatives for the nonclassical CMOS device family available to address the above issues are band-engineered transistors, resulting in improved mobility of the relevant charge carriers, and multiple-gate structures, including the vertical FinFET device. The band-engineered transistor has been briefly addressed in a previous note [41], so we will concentrate on the vertical transistor structures herein.

SOI and FinFETs

The spectrum of innovative device configurations that address transistor scaling issues includes alternative vertical transistor structural configurations where the direction of current flow is either parallel to the surface of the substrate as in the FinFET, or where the current flow direction is perpendicular to the substrate surface [27]. Often, such devices are ultrathin and fully depleted (FD), and utilize an SOI substrate. Semiballistic transport may eventually be an issue [42, 43]. One configuration posits a double-gate CMOS device with an undoped (or lightly doped), ultrathin FD SOI substrate [44]. The utilization of a double-gate configuration for dynamic Vt operation has already been discussed for DRAM applications [45]. The benefits of an asymmetrical, self-aligned double-gate CMOS device compared to a symmetrical double-gate structure have been theoretically modeled [46]. Other configurations for the ultimate CMOS silicon and end-of-the-roadmap devices have also been discussed [35, 36].


Figure 2. Schematic illustrations of transistor cross-sections for a) planar bulk, b) partially depleted (PD), and c) fully depleted (FD) SOI, courtesy of M. Bohr [47] and Intel Corp. The planar bulk and PD SOI structures still require shallow extension junctions and halo implants to control SCE, but are not illustrated herein for convenience. (Reproduced by permission of The Electrochemical Society Inc.)
Click here to enlarge image

Planar, bulk polished, and epitaxial wafers, as well as partially depleted (PD) and even FD SOI silicon materials, present short channel effect (SCE) scaling issues. SCEs become especially significant as Lphys approaches the 20nm and the sub-10nm regime. Figure 2 illustrates these various material configurations [47] and Table 1 (at end) summarizes several of their advantages and disadvantages [4, 6, 32, 47]. Figure 3 illustrates ultrathin (FD) silicon film single- and double-gate transistor structures [6, 48], with several of the relative benefits and disadvantages summarized in Table 2 (at end).


Figure 3. Schematic illustrations of transistor cross-sections for fully depleted (FD) SOI with a) single- and b) double-gate structures (based on [6, 48]).
Click here to enlarge image

In that regard, one might consider multiple-gate structures [49–51]. The concurrent utilization of multiple-gate structures may also alleviate, to some extent, the difficulties in the characterization and metrology (P/T analysis) of the silicon thickness for FD applications. That is, it appears that the FD thickness for single-gate MOSFETs is required to be as small as one-third of Lg, to control SCE [52], requiring severe P/T ratios, as generically discussed in [53] (for Lg). The multigate structures generally allow a relaxation of this thickness (1/3 Lg) requirement. It is also anticipated that various multigate configurations will mitigate the SCE [6, 48, 51]. One such embodiment is the FinFET (Fig. 4) [25, 26]. The fabrication of the fin connecting the source and drain appears to have the advantage of relatively conventional processing, largely compatible with current techniques. Nevertheless, significant issues must be addressed such as characterization of the fin doping and the surface roughness of the edge of the fin (which will degrade the effective mobility of the charge carriers in the inversion layer) and methodologies for appropriate annealing to restore the mobility.


Figure 4. FinFET structure a) perspective view, simplified, and b) top view, after T-J. King and C. Hu [25, 26].
Click here to enlarge image

The multigate structures generally allow a relaxation of the thickness (1/3 Lg) requirement. For example, Fig. 5a on p. 64 shows the silicon thickness requirement for a single, conventional planar CMOS structure in comparison to a tri-gate structure [51]. In the former case, an Lg of 20nm would require a silicon FD thickness of ~7nm, necessitating a significant P/T requirement. On the other hand, the tri-gate structure theoretically relaxes the critical silicon body thickness to approximately Lg, inasmuch as the inversion layer is being formed via three surfaces. In a similar manner, even a double-gate structure offers P/T relief as the silicon body thickness is increased to about 2/3 of Lg, although the tri-gate structure offers further P/T relief. (See Fig. 5b [51]; note in this case the body thickness for the double-gate case is represented by the symbol WSi). Other related configurations such as the omega (Ω) gate have also been discussed [54]. Measurement of the fin dimensions is a significant characterization issue for such advanced device structures.


Figure 5. Tri-gate relaxes a) TSi requirement of single-gate, and b) WSi requirement of double-gate. (Courtesy of R. Chau [51] and Intel Corp.)
Click here to enlarge image

In a more far-reaching sense, one may consider the fin of the FinFET as a quantum wire MOSFET [55], in conjunction with the frontend fabrication approaches briefly noted earlier such as high-k gate dielectric, metal gate, and low-resistance source and drain in conjunction with a FD SOI substrate material (strained Si may also be utilized). Furthermore, there appears the opportunity for multiple fins, with multiple gates as appropriate, increasing the total source-to-drain current, although the minimum spacing of adjacent fins will depend on the implant angle of the S/D doping.

The relative immaturity of SOI materials compared to bulk and epitaxial silicon, however, will result in significant challenges for the understanding of SOI specific defects and their impact on device performance and yield in a production environment [56–59]. For example, gettering methodologies will be a significant issue for SOI [60, 61]. The reduced quality previously seen with the BOX layer on SIMOX, compared to a conventionally formed SiO2 layer, has suggested an enhanced transport of Fe through the SIMOX BOX layer [62]. A similar phenomenon has also been reported for Cu and Ni in SIMOX wafers [63]. Metrology methods for many of the SOI defect categories require destructive chemical etching that decorate but do not uniquely distinguish various types of crystal defects. These various defects may not all have the same origin, size, or impact on device performance and yield, and thus may exhibit different effects on degrading or killing device characteristics. Nondestructive and fast-turnaround methods are needed for measurement of the electrical properties and the associated structural defects in SOI materials. The role of the background interstitial oxygen [64] and substitutional carbon [65] in the starting CZ material are also issues that will need to be comprehended. Clearly, this is an area that will require significant further research, especially with the various forms of BOX being explored.

Metrology for SOI wafers is also a significant challenge. One critical example is the assessment of SOI material properties with an edge exclusion of 2mm per the ITRS. The particle metrology readiness grades for general polished and epitaxial wafer characteristics are not applicable for SOI wafers. Interference effects arising from multiple reflections from the Si and BOX layers fundamentally alter the response of optical metrology tools compared to polished and epitaxial wafers, generally degrading the measurement capability. For instance, the current particle size capability for SOI wafers is 120–150nm as compared to 90nm (for polished and epitaxial wafers) for the 90nm technology generation in a production fab, although 65nm particles can be routinely measured for these wafers on current tools. The anticipated shift from capacitive to optical measurement of wafer site flatness beyond the 90nm technology generation appears to have been resolved for site flatness measurements. The characterization and metrology issues for the various strained silicon configurations (spatially varying Si:Ge composition content, threading dislocations, misfit dislocations, and associated defects, as well as unique surface roughness issues) will require significant attention [26, 66–68]. It should also be noted, however, that in-line transistor fabrication process techniques to generate local strain in silicon — e.g., isolation, source-drain contact technology, gate stack layers — are also being investigated by various IC manufacturers; see [69] for an example.

Prognosis

The drive to service a broad variety of leading-edge IC applications such as microprocessors (MPUs), servers, smart power, and RF signal processors [3] has concurrently been accomplished utilizing a variety of SOI fabrication methodologies [32, 41], which, in conjunction with high-k gate dielectrics, metal electrodes, elevated source-drain, strained silicon layers achieved by a host of methodologies and eventually, perhaps, FinFET structures, will drive us to the ultimate CMOS device structure. The applicability of SOI materials for these leading-edge IC applications appears warranted in the recovery of the growth expectations anticipated with Moore's law and the ITRS, especially with 3D device configurations [70–73], resulting in a large number of unique device configurations. As noted earlier, the assessment of productivity gains, whether by staying on the productivity curve or increasing manufacturing effectiveness, may have to be expanded. Rather, modeling productivity — the identification of new productivity measures — will be required [74].

Finally, it may be appropriate to briefly note that several alternative novel device structures beyond CMOS have been described [35]. In any case, it seems that these alternatives will need to be capable of integration with Si-CMOS for maximum leverage, to operate at room-temperature with the capability of system-on-chip (SOC) applications, including gigabytes of memory storage, and to meet the needs of portable gear (ensuring the opportunity for a mass, commercial market). One such example is a molecular single-electron latching switch between gold nanowires, which has been described in conjunction with an SOI MOSFET integrated system [75]. Significant opportunities for silicon-based ICs will continue for at least the next 100 years [76], certainly for volume production, which may not necessarily always require state-of-the-art design rules, including combinatorial configurations with alternative novel devices beyond CMOS.

Conclusion

Planar MOSFET device scaling has taken the IC industry from the realm of physical gate lengths of, for example, 7.5µm for the 4K DRAM to about 37nm for the high-performance MPU for the 90nm technology generation. Scaling has been the driver in meeting the projected overall chip performance, density, and power requirements. Different end-user applications such as a high-performance MPU or a low standby-power device will, of course, require different metrics. Frontend material and process solutions will include high-k gate dielectrics, metal gate electrodes, elevated source/drain, spike annealing and, eventually, novel source/drain doping and annealing procedures as well as strained silicon and SOI. The assurance of continued scaling to the 18nm technology generation (Lg = 7nm) or so appears soluble within currently understood physical principles [4–6, 21]. Effective nonplanar solutions must rectify significant process issues for vertical transistors in conjunction with multiple-gate and FD SOI, in some combinatorial mix. The ultimate CMOS MOSFET with Lg < 10nm may be a lightly doped channel (strained silicon or germanium, although germanium's device performance may be somewhat limited due to its smaller energy-gap than silicon), ultrathin (FD) FinFET (with multiple fins and multiple gates), in conjunction with the high-k gate dielectric, metal gate electrodes (approximately mid-gap work function), elevated source and drain, etc. Beyond that regime, however, an emphasis on alternative novel device structural configurations may be essential for state-of-the-art design rule applications [35, 75, 77].

In reality, however, each IC manufacturer will utilize that portion of the potential manufacturing process tools and device structures available to ensure their optimal participation in the particular markets they serve. Perhaps our IC industry has been best described by Gordon Moore, who has recently noted: "...and you are once again reminded that this is no longer just an industry, but an economic and cultural phenomenon, a crucial force at the heart of the modern world" [78]. Indeed, Moore has noted that "no exponential is forever: but 'forever' can be delayed" [79], which could account for the IC community's drive to maintain the pace of Moore's law.

Acknowledgments

The authors appreciate discussions and the utilization of a number of figures for both the manuscript (and the oral presentation) from M. Bohr, D. Buchanan, D. Chapman, R. Chau, J. Chung, R. Cleavelin, J.-P. Colinge, M. Currie, P. Gargini, E. Gusev, J. Hergenrother, J. Hoyt, C. Hu, J. Hutchby, T.-J. King, K. Likharev, G. Lucovsky, V. Misra, T. Mizuno, S. Monfray, P. Mooney, Y. Nishi, C. Osburn, G. Parsons, D. Schlom, T. Skotnicki, B. Wallace, G. Wilk, R. Wise, and F.-L. Yang. The assistance of both the FEP Division and fab personnel at International Sematech and our colleagues at the FEP-RC, IMEC, ASM, and AMAT is also appreciated.

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Howard Huff received his PhD from MIT in 1966 and is currently a Senior Fellow at International Sematech, 2706 Montopolis Drive, Austin, TX 78741; ph 512/356-3334; e-mail [email protected].

Peter Zeitzoff received his PhD from Princeton U. in 1976 and is currently a Senior Fellow at International Sematech; e-mail [email protected].

Material in this abridged/edited article was originally presented at the 2003 International Conference on Characterization and Metrology for ULSI Technology. Reprinted with permission from AIP Conference Proceedings 683(1), pp. 107–123, 2003. Copyright 2003, American Institute of Physics.

Table 1. Brief comparison of the various transistor types*

Planar bulk

  • Advantages
    • Wafer cost/availability
  • Disadvantages
    • SCE scaling difficult
    • High doping effects and statistical variation
    • Parasitic junction capacitance

Partially depleted SOI

  • Advantages
    • Lower junction capacitance
    • Floating body performance improvement by device and circuit design; elimination of "body effect" in planar bulk
    • 20–25% reduced process time and improved manufacturing "ease" compared to planar bulk
    • 25–35% improvement in device performance compared to planar bulk
    • Reduction in chip power by 1.7–3.0× compared to planar bulk
    • Lower soft-error rate compared to planar bulk
    • Recovery of Moore's law growth projections
  • Disadvantages
    • SCE scaling difficult
    • Floating body and history effects
    • Wafer cost/availability
    • High doping effects and statistical variation

Fully depleted SOI

  • Advantages
    • Lower junction capacitance
    • Operational beyond 300°C
    • Threshold voltage and leakage current less sensitive than planar bulk
    • Improved swing leading to lower off-current
    • No floating body and history effects
    • Less dependence on device and circuit design
    • Multiple-gate structures alleviate need for ultrathin SOI
    • Lower soft-error rate compared to planar bulk
    • Recovery of Moore's law growth projections
  • Disadvantages
    • SCE scaling difficult
    • High source/drain series resistance
    • Sensitivity to silicon thickness (ultrathin SOI) to ensure acceptable DIBL
    • Source/drain contact requires thickened silicon, compared to ultrathin body, to decrease series resistance
    • Wafer cost/availability
*Refs 4, 6, 32, 47

Table 2. Brief comparison of single- and double-gate SOI transistors*

Single gate

  • Advantages
    • Lower junction capacitance
    • Reduced channel doping for metal gate electrode, fully depleted
  • Disadvantages
    • SCE scaling difficult
    • Sensitivity to silicon thickness
    • Wafer cost/availability

Double gate

  • Advantages
    • Enhanced scalability
    • Near ideal subthreshold slope S
    • Lower junction capacitance
    • Reduced channel doping for metal gate electrode, fully depleted
    • About 2× drive current for symmetric gate
    • Asymmetric gate capability for dynamic Vt operation
  • Disadvantages
    • Complex process
    • Wafer cost/availability
    • About 2× gate capacitance
    • Advanced device structure, difficult to fabricate at present
*ultrathin silicon film, fully depleted; Refs. 6, 48