Removing copper over low-k films using stress-free polishing
08/01/2004
With the convergence of chemical mechanical planarization (CMP) and low-k dielectrics for copper dual-damascene interconnects at the 130nm technology node and below, the low mechanical strength of low-k films can cause delamination when using conventional CMP [1]; the potential for delamination will be even greater as IC manufacturers adopt increasingly porous ultralow-k films. Evaluation has shown that stress-free polishing (SFP) can eliminate this concern.
Stress-free polishing is a low viscosity fluid contact alternative to CMP that enables the removal of copper overburden without exposing barrier or dielectric films to mechanical stress, which is a principle cause of delamination [2–3]. Briefly described, SFP applies a voltage where the wafer processed is the anode held in an electrolyte. The process removes copper from the wafer through control of wafer rotation, recirculating electrolyte flow, and voltage and current; slurry is not used. A proprietary endpoint technique stops this "copper polishing" process at the underlying metal-barrier film. Two key characteristics of copper removal with SFP are high selectivity with respect to barrier films (Ta or TaN) and its isotropic nature.
Our evaluations used single-damascene, short-loop wafers patterned with a MIT854 mask or an in-house LSI mask. The dielectric was a multilayer TEOS-SiC-SiOC stack on silicon. The barrier-film and seed copper layers were deposited via physical vapor deposition, and copper electroplating was used to fill the trenches.
Because the SFP process is inherently isotropic with no planarizing capability, topography on wafers coming into this process must be minimal. There are two ways to achieve this: 1) by a partial CMP step or 2) by reducing topography variation through modification of masking. The latter was accomplished by modifying the mask layout with insertion of dummy metal in wide-field areas and dielectric posts in wide metal trenches.
After using one of the two methods mentioned above, the remaining copper was cleared using SFP and the barrier film removed by plasma etching; for the evaluations reported here, ACM Research did all plasma etch processing on a single-chamber manual-load system in its development lab.
LSI Logic performed visual inspections, top-down SEMs and AFMs for topography before and after barrier removal. All electrical and structural characterizations were after barrier removal.
The initial SFP process development work was accomplished with wafers having a blanket copper layer to characterize the removal rates of copper as a function of power, chemical flow rate and other process parameters. Short-loop patterned wafers were then used to determine the performance of the polishing technology and the process was compared to LSI Logic's current standard CMP process.
Topography's effect
Applying SFP directly to post-plated wafers isotropically removes the deposited copper even down into trenches wider than 2µm. A series of partial-CMP experiments were performed to find the right copper-film thickness and planarity conditions that would lead to successful application of the polishing step. Figure 1 shows the evolution of topography for varying trench widths at 50% density for post-ECP, pre-SFP (or post-partial CMP), post-SFP, and post barrier removal. Positive and negative values indicate over-plated copper and recessed surfaces, respectively.
 Figure 1. Topography reduction after copper electroplating in preparation for SFP, 50% trench-density structures. |
The SFP process endpoint detection stops the process at the barrier metal; the subsequent plasma-etch step removes the barrier film. Topography values were correlated to the amount of copper loss in trenches; copper loss in trench widths >1µm were significantly higher than from narrow trenches.
Incoming planarity
Both the partial CMP and mask modification methods of altering incoming planarity resulted in planar prepolish topographies. For example, insertion of dielectric posts had at least a 5× reduction in the postplating and postpolish dishing values for a 100µm pad.
 Figure 2. Comparison of normalized topography for varying pre-SFP processes; a different mask was used between direct SFP and SFP plus CMP. |
Figure 2 shows topography data from four sets of wafers processed: three sets planarized to different incoming pre-polish topography using partial CMP and one set processed without CMP. The mask layout on wafers without CMP included strategic dummy metal and dielectric slot insertion. The maximum incoming topography prior to SFP was 1000Å, 500Å, and 200Å for wafers processed with "partial CMP1," "partial CMP3" and "partial CMP2," respectively (see Fig. 2). Variation in post-barrier topography was the least with the polished wafers processed with "partial CMP2" and with the modified mask.
 Figure 3. Tilted SEM image of modified layout at post-SFP without an intermediate planarization step. |
These tests showed that good interconnect results with SFP can be obtained using either an optimized partial-CMP or smart dummy metal-dielectric post insertion (Fig. 3). Insertion of dummy dielectric posts in wide metal trenches reduced copper loss significantly. For example, in a 100µm pad, without the insertion of dielectric posts, all copper is removed in the polishing process. With dummy dielectric posts, however, 65% of the copper is retained in these pads. The final copper thickness in the trench was less for isolated features than for dense arrays because of micro-loading effects. Insertion of dummy metal features adjacent to the isolated line was effective in significantly reducing copper loss.
Inspection and electrical results
Wafers were inspected using various optical, SEM and FIB techniques, verifying that the field area did not have any metal residue (copper or barrier, Fig. 4). In addition, FIB analysis of bridging structures showed copper recessed along trench walls and a higher elevation dielectric surface between trenches indicating high etch selectivity of Ta-TaN to dielectric.
 Figure 4. Top down SEM images of bridging structures showing no metal residue (left) and X-SEM (right) of metal trenches. |
Electrical tests on all wafers found good correlation to topography data. Data in Fig. 5 compare a) bridging and b) continuity for 0.16µm trenches; the data sets compare two lots of wafers processed completely with CMP (using two different consumable supplies) with three lots of wafers processed with SFP. There were no bridging failures for either set of "full CMP" data and the median resistance was lowest for wafers processed completely with CMP. The data for the SFP-processed wafers, however, show that wafers with the lowest incoming planarity had the lowest median resistance value. The increase in leakage associated with the SFP-processed wafer was traced to plasma damage on the dielectric film created during barrier film removal. The barrier etch process is now being optimized to eliminate this problem.
 Figure 5. Bridging a) and continuity b) data for 0.16µm trenches. |
The sheet resistance of copper trenches processed by SFP remained constant over a wide range of pattern density. The loss of copper in isolated lines was very high; in the absence of any partial CMP, copper was completely removed in lines wider than 2µm. The final copper thickness in trenches was less for isolated features than dense arrays because of micro-loading effects. Inserting dummy metal features adjacent to an isolated line was effective in reducing the copper loss significantly.
Conclusion
Stress-free polishing has been shown to be a viable, evolving alternative to CMP in IC fabrication; in the studies described above, no damage on low-k films was observed when using it to remove copper. A key element to successful application is preprocessing and pattern modification that optimizes the wafer's topography to the polishing process. It was demonstrated that pattern modification enables successful SFP without an intermediate CMP step. Further, micro-loading effects that cause varying results can be minimized by inserting dummy-metal features in circuit patterns. Optimization of both SFP and the associated plasma etch process are in progress at LSI Logic.
Acknowledgments
Co-authors for this article are: Leo Kwak, Sam Gu, Cary Falk, Michael Lu, Sey-Shing Sun, Jim Elmer, Steve Reder, Rob Donis, Lesly Duong, and Peter Wright from LSI Logic Corp., Gresham, OR; and Bill Hannan, Fred Ho, Danielle Zhang, and Jian Wang from ACM Research Corp., Fremont, CA.
The authors from LSI Logic thank ACM Research for equipment and process support, and enabling the plasma etch process work at its facility. The authors also thank members of the Advanced Process Module Development group at LSI Logic and Richard Schinella and Wilbur Catabay for ongoing support. SFP is commercially available as the Ultra-SFP tool. Ultra-SFP is a registered trademark of ACM Research.
For more information, contact David Wang, ACM Research, Fremont, CA 94538; ph 510/445-3700, ext. 101, [email protected].
References
- 2001 CMP-MIC Conference 600P/00/0349 by CMC and ISMT.
- David Wang, et al., "Stress Free Polishing Advances Copper Integration with Ultra Low-k Dielectrics," Solid State Technology, pp. 101–106, Oct. 2001.
- J. Pallinti, et al., "An Overview of Stress Free Polishing of Copper," International Interconnect Technology Conference, June 2003.