How Taiwan's foundries have closed the gap with IDMs
08/01/2004
In less than a decade, the dynamics between Taiwan's large silicon foundry base and leading integrated device manufacturers (IDM) have shifted dramatically. No longer lagging the IDMs by at least one process generation — as had been the case in the 1990s — Taiwan's pure-play foundry giants are now running neck-and-neck with leaders in shipping advanced IC technologies out the door.
The technology gap closed between the 0.18µm, 0.13µm, and 90nm process generations as the foundries accelerated their R&D to meet the demands for more complex ICs from the world's growing and aggressive fabless semiconductor sector. In fact, many in Taiwan's chip industry now predict that the pure-play foundries will be the first to provide 65nm processes to customers on 300mm wafers.
Much of the success of Taiwan's foundry industry can be linked to the timing of capacity additions and sharply focused R&D investments in manufacturing technologies. By targeting support for leading-edge fabless customers, pure-play foundries have been able to accelerate manufacturing learning curves and process technologies to reach parity with the world's top IDMs.
Historically, IDMs have had an advantage in being able to address development of IC architectures, circuit designs, wafer processes, and assorted manufacturing challenges simultaneously and under one operation. However, rapidly escalating costs in building new wafer fabs have put chipmakers under tremendous pressure. Meanwhile in the 1990s, the fabless semiconductor model proliferated because it allowed IC suppliers to focus on product design instead of building billion-dollar plus fabs.
 A UMC fab worker loads a 300mm tool while other wafer carriers are transported overhead to various process bays. |
The growing success of the fabless model also triggered its own changes in the semiconductor-manufacturing segment. As fabless chip houses pressed harder to use leading-edge processes for systems-on-chip (SoC) and other products, they needed new manufacturing sources but were also reluctant to provide proprietary design information to competing IDMs. Therefore, fabless companies turned to pure-play foundries seeking more advanced processes. As a result, Taiwan's silicon foundries began accelerating investments in leading-edge plants and technologies, which then helped to level the field with IDMs in the last three process generations.
The 0.13µm process generation proved to be a key turning point for chip foundries trying to clear major technical hurdles and move into leading-edge nodes. There were many false starts as the industry debated which low-k dielectric materials were best for 130nm ICs, or whether fluorosilicate glass (FSG) were a safer interim step for dual-damascene copper interconnect processes. The choice and integration with copper metal posed a huge challenge for Taiwan's major foundries at the 0.13µm node.
The issues encountered at 0.13µm did come with a silver lining. Learning curves from that process node are being fully leveraged at the emerging 90nm generation because foundries have maintained similar process steps in the new technology. Consequentially, the foundries are projecting smoother ramp rates for 90nm ICs on 300mm wafers. In fact, 90nm tapeouts of designs for foundry fabs began rolling out shortly after 0.13µm processes ramped to high volume in Taiwan.
To help foundry customers leverage new deep submicron processes, UMC has expanded partnerships with supply-chain vendors. Instead of treating electronic design automation (EDA), intellectual property (IP) libraries, and other segments at arm's length from foundry services, stronger partnerships have pooled knowledge and know-how together. This has enabled design kits, design flows, IP elements, and EDA tools to work in harmony with customer development practices and foundry process technologies.
For example, UMC has worked with its supply-chain vendors to provide silicon-verified reference flows and a broad spectrum of third-party IP components (such as memories, analog/mixed-mode components, consumer cores, microcontrollers, and microprocessors) that are optimized for interoperability and manufacturability in advanced processes. These efforts have greatly eased customer concerns regarding the creation of new components or flows, or retargeting existing ICs in new processes or SoC implementations.
 Technical check on a 300mm wafer tool in UMC's Fab 12A. |
Currently, 0.13µm and 90nm are the most advanced mainstream production technologies running in fabs. 65nm processes are well under development, however, and many companies — including major foundries, like UMC — expect the introduction of this next-generation technology sometime in early 2006. Much effort is being made in R&D for the development of key enabling technologies, such as high-k gate dielectric, low-k intermetal dielectric, strained silicon, and silicon-on-insulator (SOI), for circuit-performance enhancements in addition to advanced optical lithography scaling at the 65nm node.
The parity between Taiwan's leading foundries and the world's major IDMs isn't confined to process technology development. The foundries have also gained ground in the move to 300mm wafer manufacturing. Taiwan's foundries have made significant investments.
For example, UMC's Fab 12A in Tainan was Taiwan's first 300mm fab to reach volume production, and it is now expected to produce more than 20,000 wafers/month by the end of 2004. In addition, Singapore-based UMCi is expected to be capable of producing more than 10,000 300mm wafers/month by year's end. This level of early 300mm maturity means foundry customers can immediately realize dramatic gains in productivity (even more for larger die-size chips) on large-diameter wafers with leading-edge processes and low defect densities due to fewer wafer edge effects.
Fabless semiconductor companies are also pushing for greater production volumes, larger die sizes, and advanced process technologies. With this comes greater concern from customers about the potential for "silicon re-spins." The cost of a product's photomasks is increasing rapidly as process geometries shrink in the 0.13µm and 90nm nodes. Therefore, foundry customers must be sure that their designs are correct before committing to full mask sets. Multiproject wafers (MPW), such as those offered in UMC's Silicon Shuttle program, help customers by making design prototypes with shared masks and substrates. On the Silicon Shuttle, a prototype can be made alongside dozens of other customer designs and IP prototypes for silicon test runs.
Customer products have been the essential drivers pushing advanced technology, and Taiwan's pure-play foundries have turned to strategic market and technology leaders to drive leading-edge processes. For example, UMC collaborated with US-based Xilinx Inc., a leader in field-programmable gate arrays, to bring to market the world's first 90nm FPGAs with the company's Spartan-3 family of FPGAs in March 2003. In June 2004, Xilinx began shipping a second 90nm FPGA product family to early-access customers — the Virtex-4 series — using the world's first triple-oxide 90nm CMOS technology with 11-layer metal interconnect. This partnership has resulted in leading-edge FPGAs for Xilinx and validated 90nm processes for UMC — cutting across boundaries that once limited foundries to lagging technologies.
But playing at leading-edge nodes requires significant capital expenditures. For example, UMC has earmarked $2.12 billion for capital expenditures in 2004, with most of the capex going to 300mm fab expansions. About 15% of this capex, or $318 million, is slated for R&D (see figure). This level of expenses dwarfs the investments made by foundries 10–15 years ago.
 UMC R&D spending and revenues. From 1997–2001, total R&D spending was $743 million. Average R&D/sales percentage was 9.1%. |
Looking ahead, one of the biggest questions facing Taiwan's foundry industry is the rapid emergence of chip manufacturing in mainland China. At least for the near future, the potential of market share moving to China's foundry industry isn't a major concern in Taiwan. While labor costs on the mainland are lower, other more important factors will dictate where wafers are processed, including overall productivity, cycle times, quality of service, technology leadership, experience, and support by established foundries.
While there is a potential for lower costs in China, poor yields and manufacturing cycle times could offset any savings by customers. China's new fabs are also at a disadvantage to compete with Taiwan's mature fabs with mostly depreciated equipment cost for mature technologies including 0.35, 0.25, and even 0.18µm technology.
Taiwan's foundry segment is also driving new technologies to further lower costs. For example, UMC is the first pure-play silicon foundry to join the X Initiative consortium, which advocates diagonal interconnect lines instead of traditional right-angle ("Manhattan") wiring layouts on ICs. This approach promises to reduce the number of vias on ICs by more than 30% and cut interconnects by more than 20%, along with lowering power dissipation. UMC has begun accepting X Architecture designs for fabrication at 0.18µm, 0.15µm, and 0.13µm processes.
Another key milestone at UMC was the successful production of the first foundry wafers using chromeless (Cr-less) phase-shift mask (PSM) technology for functional customer products at the 90nm node. UMC is considering Cr-less PSM technology to apply 193nm wavelength lithography to 65nm processes. With the Cr-less approach, UMC has achieved improved CD uniformity and line-edge roughness control, meaning that layout patterns are more accurately printed on silicon.
This technology uses two phase edges instead of one to define single-line patterns. The contrast of the image is enhanced through destructive interference at each phase edge, which leads to enhanced gradient of exposure intensity. This approach results in improved resolution and CD control in advanced lithography processes, based on UMC's work.
 A fab worker expedites a wafer lot in UMC's 300mm fab. |
The Cr-less technology is also proving to be more cost effective in manufacturing than the alternating PSM approach, which requires double exposure and two masks for each patterning layer. UMC is now evaluating the use of Cr-less PSM technology beyond the 65nm process node, along with several other resolution-enhancement technique candidates.
On the IC design side, UMC has developed an electromagnetic design methodology (EMDM) for radio-frequency CMOS devices. This design approach uses a combination of electromagnetic analysis tools working together to reduce simulation cycle times from hours to just minutes. The new methodology effectively eliminates what has traditionally been a tremendous time- and resource-intensive commitment for RF designers.
The methodology was also created to greatly reduce overall development cycle times and costs for customers designing RFCMOS ICs. The EMDM allows engineers to easily and accurately create any RF structure, such as spiral inductors, in their designs without going through several wafer splits and the painful tasks of measurement, data fitting, and modeling.
New initiatives are also underway in the foundry segment to support design-for-manufacturing (DFM) solutions. It is becoming increasingly important to provide accurate device models, silicon-verified core circuits, and IP, especially for analog and mixed-mode applications. Foundries are working more closely with EDA software vendors and customers to speed the implementation of low-power IC designs in next-generation processes.
More silicon-verified IP design cores are becoming available, and foundries are offering online services to closely track products as they move through factories. One thing is certain: the foundries are moving full-speed ahead.
Fu Tai Liou received his PhD in material science and engineering from the State U. of New York at Stony Brook, and also graduated from National Central U. in Taiwan and received his MS in physics from Auburn U. He is the head of the America Business Group at United Microelectronics Corp., No. 3, Li-Hsin Road II, Science-based Industrial Park, Hsinchu City, Taiwan 300, R.O.C.; ph 886/3-578-2258, fax 886/3-578-4308, e-mail [email protected].