Technology News
07/01/2004
Bonding wafers with microbumps produces SoC performance
Sony Corp. says it has achieved system-on-a-chip performance by bonding separate chips together with solder microbumps, in a type of system-in-a-package verging into a simple variant of stacked-wafer 3D circuitry.
The company has bonded a microprocessor onto a DRAM chip, with 1300 signal pins with data transfer speeds up to 160Gbits/sec, matching the performance of a single-chip embedded DRAM system, without the complications and costs of developing and producing the one-chip version (see figure).
 Sony has joined the microprocessor directly to the DRAM with microbumps. (Sources: Sony, Nikkei Microdevices) |
From the beginning, the developers tried to think of the two chips as one system, optimizing the design to minimize the circuits that would be needed to connect the chips. Then they reduced resistance by making the connections themselves as small as possible.
The chips are joined by microbumps 30µm dia. and 16µm high on each chip, which flatten more upon bonding the chips together. That brings resistance down to 14mΩ/bump, and capacitance down to 50fF/bump, or about the same range as a 1mm circuit on one chip, bringing the speed and power usage of the two joined chips down to about the same as one chip.
Sony says the bumps themselves involve no special technology, but are simply made from standard lead-free SnAg solder. But to get reliable connections, they worked on controlling the bumping process to reduce variability in the tiny bumps' dimensions, and improved positioning accuracy.
Chip designers had to use an EDA environment that could treat the two chips as one at first to optimize total system design. Then from the mask layout phase, the DRAM and microprocessor were treated separately for best pin placement.
"This made it possible to make the circuit length between the chips as short as possible," comments Teruo Hirayama, general manager of applied technology for Sony Semiconductor Solutions Network Company's technology development group.
Prototype connected chips met the goal of 123MHz or better performance at 1.5V.
The units were also designed for testing. Since the microbumps are too small for direct probe contact for testing, the chips included test circuitry for scanning for signals from each bump.
Though SoCs will remain the better choice for high-volume applications, Sony suggests this approach for combining different types of chips could be better for lower-volume uses requiring more variations, and would allow easy memory upgrades. The company sees applications for its graphics processors. — SST partner Nikkei Microdevices
"Solid First" processing: a new approach to low-k?
Getting to a lower effective dielectric constant, or k values below about 3, is proving troublesome due to integration issues. It has been hard to isolate pores, and inclusions have raised k values over time even with sealing to prevent diffusion during post-processing. Pores also lower mechanical strength, causing problems in subsequent CMP and packaging steps.
Rohm & Haas's Electronic Materials, Marlborough, MA, has developed a new approach called "Solid First" processing, using a material called Zirkon for interlayer dielectric (ILD). It avoids releasing the poragens (embedded polymers that are baked away) until after imaging, etching, and deposition of a barrier layer, according to Philip Rose, VP, global marketing.
The Zirkon MSQ-based material is spun on and cured without heating, he explained, embedding the poragens in a solid matrix. The technique allows good mixing of the material and control of the polymer backbone so the poragens can be removed at traditional temperatures. After the barrier layer is in place, the wafer can be heated to temperatures <400°C, removing the poragens and leaving air-filled pores.
Rohm & Haas (the former Shipley group) has been working with International Sematech on developing the process for k values down to 1.8, and Rose reported there is also work on depositing multiple layers (3–4) before releasing the poragens at temperatures <400°C. This would maintain mechanical strength and avoid raising k values during post-processing. — B.H.
Breaking the sub-1Å imaging barrier by combining correction technologies
A new 200kV transmission electron microscope (TEM) from FEI Co. has an image resolution <1Å. FEI reports an image resolution of 0.8Å.
The high resolution is achieved by combining technologies that correct for both spherical and chromatic aberrations. Spherical aberration is corrected using a Cs image corrector by CEOS — a partner of FEI. Chromatic aberration is minimized (e.g., the effects of chromatic blurring) using an electron-beam monochromator developed by FEI. Together with FEI's Tecnai F20 ST TEM, the resulting system eliminates delocalization effects that occur with all microscopes, such as artifacts and blurring at interfaces.
"By using the most energetic beam for the shortest period of time, a researcher minimizes the amount of energy the sample under observation sees," explains Jay Lindquist, senior VP of corporate marketing at FEI. "By limiting the energy dose, the sample is perturbed the least during the imaging process."
Because the image is acquired directly from the TEM in real time — without manipulation, calculations, or extrapolations — it is artifact-free (see figure). The company has images of a gate oxide sample showing atom columns and silicon "dumbbells;" it is possible to see the transition from the substrate to the oxide, as well as whether or not gate columns are relaxed or stressed. — D.V.
Statistical process control may slash IC testing costs
Continuous cost savings from wafer-fab learning curves and device shrinks have targeted IC testing steps for elimination. Testing costs are now an estimated 10%–25% of average selling prices of ICs.
Newly patented software developed by startup Pintail Technologies Inc., Plano, TX, may reduce the need for chip testing by performing real-time statistical control sampling and analysis on data from wafer probe and automatic test equipment. As long as the data remains "in statistical control" (ISC), full testing of ICs can be eliminated without lowering quality, according to managers at four-year-old Pintail, which is collaborating with Texas Instruments Inc. to prove the concept for mixed-signal products.
ATE testing times and associated costs can be reduced by 40% or maybe more when mixed-signal test programs are monitored by Pintail's SwifTest software statistical control engine, say company managers (see figure). The software runs on a range of existing test platforms, including wafer probers and ATE systems.
 Test times have been reduced 45% using statistical optimization and "in control." |
Operating on the fly, the SwifTest software captures test data, performs analysis, and then decides whether the test data is "in" or "out" of ISC limits. The software does its work while testing equipment indexes and positions its test pins for the next series of devices. For wafer probers, the indexing time is typically 120 msec, while ATE test handlers take between 200 msec and up to 3 sec to index, says Jeff Bibbee, Pintail's CTO and co-founder. "There may be anywhere between 300 to a couple thousand test programs for a device, depending on the complexity. We're not proposing to sample all of those," Bibbee explains. "However, if there are 500 tests, you might be able to sample 200 to 300. Time and money can be saved."
Pintail first developed a simulator to show that test programs could be sampled in real time and eventually replaced by statistical process control (SPC) techniques. Pintail then teamed up with Dallas-based TI, which had been working on SPC software for test but found it costly to implement across a wide range of test platforms.
"The challenges include different operating systems, different test-platform environments, and different programming languages," notes Scott Bibbee, director of marketing and co-founder at Pintail. The on-line, real-time software engine was launched a year ago.
The use of SPC in wafer fabs has become an accepted way to monitor many processes, but in IC testing — especially final test — statistical control sampling remains controversial, notes Jeff Bibbee. "It is a 'religious' issue," adds Pintail's CTO, referring to conventional approaches of increasing test coverage with faster (and more expensive) ATE machines. "Test has become a greater percentage of cost. Testers generally are generations behind IC technology, so building faster and more expensive hardware is not the way to catch up," he adds.
Pintail offers the capability to determine which test programs are in statistical control using Cp and Cpk indices. (Cp describes the spread of data between defined limits using standard deviation calculations, while Cpk determines location of accuracy in the center of the range.) A Cp/Cpk rating of ≥2 will determine that a parametric test program is in statistical control and suitable for sampling. "That means the sampling will maintain six-sigma quality, or there is a 1 part per billion chance of a failure," says Scott Bibbee.
If the data shows any tests falling out of statistical control, the software will "deactivate" sampling during a test run. It can alert test engineers of a problem, and this information can be used to quickly determine the source of the failure, including potential process changes in the wafer fab. — J.R.L.
Experts debate USJ formation technology at MRS
Combine the always strong desire of IC manufacturers to extend current technology (spike anneal) as long as possible, with the growing interest in both flash RTP and SPER, as well as laser annealing, and you have a spirited debate on USJ technology among experts at the MRS Spring Meeting, recently held in San Francisco.
General agreement exists that flash lamp (millisecond) annealing and sub-melt laser annealing hold promise. "They produce comparable values of junction depth, sheet resistance, and profile abruptness, which come close to meeting the ITRS 45nm requirements," states Susan Felch, program manager, USJ development, in the parametric and conductive implant group at Applied Materials. "However, they both have technical shortcomings that must be overcome."
Jeff Gelpey, VP, semiconductor technology, at Vortek Industries Ltd., a developer of flash lamp annealing technology, sees flash anneal as having advantages: higher throughput and less lateral temperature gradient in the wafer because the entire surface of the wafer is heated at the same time in the flash approach, as well as the use of an intermediate temperature step.
SPE has some challenges, though, adds Gelpey: "The process integration issues are formidable, and the leakage issue will remain important except for some high-performance devices." He cites the ability to use existing process tools and ease of implementation as pluses.
"There are still more questions than answers regarding both millisecond annealing and SPER — suggesting that neither approach may be mature enough for the needs of volume production at the 65m node," says Paul Timans, director of technology, RTP product business unit, at Mattson Technology Inc. "Conventional RTP will continue to be essential." One driver for SPER is the desire for low-temperature processing conditions that may simplify incorporation of advanced materials (metal gates, high-k dielectrics) that will be needed at the 45nm node. "But the process integration [for SPER] requires significant changes from the current practice and the effects of residual damage are still a concern," says Timans.
"SPER techniques may face additional challenges with the advent of thin SOI and multigate architectures because the amorphizing implants must leave a residual crystalline seed for the SPER process — control of this aspect could be a tough challenge in ultrathin silicon films," adds Timans.
John Borland, founder of J.O.B. Technologies, summarizes his findings after visiting several IC manufacturers: "Most every company I spoke with is extending spike/RTA to the 65nm node or a combination of SPE and spike/RTA." He observes that laser annealing, like flash, is delayed until the 45nm node at the earliest. "Everyone is beginning to realize that whenever you have PAI, SPE will always occur during the wafer heat-up." As a result, Borland notes that IC manufacturers can do a lower-temperature pre-anneal between 500–700°C before a 1200–1350°C flash millisecond anneal.
One process option, plasma doping, doesn't share widespread acceptance. "Conventional beamline implantation has always been able to do the job, and the potential cost savings of plasma doping has never justified the risk of a new technique," notes Gelpey. "With the sharper implanted profiles for USJ, this might change."
Borland sees no technical advantage with plasma doping, though it has a productivity advantage. "But there are issues and alternatives such as using molecular species (e.g., B10H14 or B18H22), being developed by Nissin and SemEquip that can be used on beamline implanters."
"[Plasma doping] seems to provide significant benefits in the ultralow-energy implant era and indeed, it has been suggested that it could be important for multigate devices with sidewalls that need to be implanted," says Timans. "PLAD implants also provide benefits in terms of the shape of the implanted profile, which is more 'box-like' than that of conventional implants."
 SIMS profile showing the results of a recipe combining a Ge+ pre-amorphization, an F+ co-implant, and an ultralow-energy B+ implant. (Source: Applied Materials) |
One strategy — co-implants — will enable spike anneal to be used for at least one more generation, says Felch. An example of a co-implant recipe that Felch says produces a USJ that satisfies ITRS 90nm requirements uses the combination of Ge+ pre-amorphization, an F+ co-implant, and an ultralow-energy B+ implant (see figure). "Other co-implant recipes show promise of pushing toward the 65nm requirements." — D.V.