Issue



Sub-1nm EOT scaling for high-k/metal-gate stacks


07/01/2004







The aggressive scaling of advanced devices has necessitated the search for a suitable high-k gate dielectric. A material is needed that provides the required specific capacitance at a considerably larger physical thickness than SiO2. As such, the gate-leakage current can be reduced by suppression of direct tunneling.

The implementation of high-k dielectrics to obtain transistors with at least comparable performance as those with SiO2 has proven to be challenging. Recent findings indicate that the HfO2-based high-k dielectrics, currently among the leading candidates, react with polysilicon, the standard electrode material. Issues with the threshold-voltage control, due to Fermi-level pinning, inferior electrical properties in terms of transistor drive current and stability, and reduced yield, have been reported by various research groups [1].

Solutions to reduce the HfO2/polysilicon interaction include the use of composite dielectric structures (e.g., using Al2O3 or Hf-silicates, or the implementation of a capping layer between polysilicon and HfO2). These techniques were found to be only partially successful, and often decrease the overall capacitance of the gate stack because of the lower k value. Although potentially useful for low standby-power applications, this approach strongly reduces the potential for scaling the equivalent oxide thickness (EOT) to values <1nm.

An alternative way to solve this issue is to replace the commonly used polysilicon electrodes with metal gates. The use of metal gates allows an additional improvement in device performance because they avoid polysilicon depletion that reduces the equivalent inversion capacitance. The replacement of both the gate dielectric and polysilicon gate electrode introduces its own set of manufacturing and reliability challenges and requires the development of specific process modules and adequate integration schemes.

First results

In exploring the concept of metal gates for use in high-k gate stacks, IMEC has produced first results that provide clear indications that metal-gated devices outperform their polysilicon-based counterparts in terms of electrical performance. High conductance, low leakage, and reduced threshold-voltage instabilities were observed for these devices. The results encourage us to believe that solutions to overcome the 'red brick wall' can be provided and the ITRS requirements for future technology generations are within reach.


Figure 1. Figure-of-merit for a) both n and b) pFET performance representing gate leakage (Jg) as a function of performance; the symbols represent performance trend lines for poly/SiO2, poly/high-k, and metal/high-k gate stacks.
Click here to enlarge image

After these results, it was clear that the full potential of these advanced gate stacks was not yet fully realized and further improvements in performance could be obtained by using optimized process flows. IMEC is therefore developing various optimized processes on the gate-stack level, as well as processes for the fabrication of short-channel transistors with etched metal gates.


Using TiN or TaN gates and HfO2 as a dielectric, aggressive scaling down to 0.8nm EOT has now been demonstrated in both nMOS (8.2Å EOT) and pMOS (7.5Å EOT) transistors. To achieve sub-1nm EOT scaling, appropriate interfacial oxide control both prior to and during high-k deposition was required. The lowest EOT values were typically obtained using a 'zero-interface approach' (i.e., minimal EOT contribution) achieved by the use of scaled chemical oxide interfaces with controlled thickness and precisely controlled deposition and annealing conditions.


HfO2 was deposited by atomic-layer chemical vapor deposition (ALCVD). Besides eliminating gate depletion, the results show enhanced high-k scalability for metal gates compared to polysilicon gates. Significant gate-leakage reduction — typically up to three orders of magnitude — has been obtained with the metal-gated/HfO2 transistors as compared to the polysilicon/SiO2 stacks.


Figure 2. Using the time-resolved ID-VG technique to compare a) poly gates (HfO2-based gate dielectrics) with b) the improved VT instability achieved with metal gates.
Click here to enlarge image

Flatband voltages were close to their ideal value of -0.27V and 0.60V for nMOS and pMOS with TiN electrodes, respectively, indicating a low charge density in the film and a good control of the gate-metal work function. Compared to their counterpart devices with polysilicon gates, a significant improvement in transistor drive current was observed. In general, electron mobility tends to degrade with EOT scaling due to increased interactions between the high-k layer and the transistor channel. However, for the engineered gate stacks under study, excellent nMOS performance was demonstrated with performance indicators slightly exceeding those for poly/SiO2-based devices (Fig. 1).


Since hole mobility remained constant down to the lowest EOT values, significantly improved pMOS performance was obtained. Not only was the initial performance improved, but threshold-voltage instabilities due to trapping, as measured with a time-resolved ID–VG technique (Fig. 2), were strongly reduced compared to typical results on high-k films with polysilicon electrodes [2]. These fast-transient techniques are a more severe test than the conventional DC techniques since they also capture the fast traps in the high-k dielectric. This indicates that higher-quality gate stacks can be produced with metal gates and brings the expected long-term performance of these gate stacks within the ITRS specifications.

Conclusion

These results have demonstrated the potential of high-k dielectrics and metal gates for sub-1nm EOT scaling and have shown that the necessary technology and understanding are currently available to further develop real solutions for advanced gate stacks that comply with the roadmap requirements for next-generation technologies. Tremendous progress, especially in terms of transistor drive-current performance and threshold-voltage stability, has brought the concept of high-k metal-gated devices for both high-performance applications and low standby power close to real implementation.

Acknowledgment

ALCVD is a trademark of ASM International.

References

  1. C. Hobbs, L. Fonseca, V. Dhandapani, S. Samavedam, B. Taylor, et al., "Fermi Level Pinning at the PolySi/Metal Oxide Interface," Symposium on VLSI Technology, 2003, Digest of Technical Papers, pp. 9-10.
  2. A. Kerber, E. Cartier, L.Å. Ragnarsson, M. Rosmeulen , L. Pantisano, et al., "Direct Measurement of the Inversion Charge in MOSFETs: Application to Mobility Extraction in Alternative Gate Dielectrics," Symposium on VLSI Technology, 2003, Digest of Technical Papers, paper #12A-1.

For more information, contact Marc Heyns, currently an IMEC fellow and department director at IMEC, Kapeldreef 75, 3001 Leuven, Belgium; ph 32/16-281-467, fax 32/16-281-637.