Issue

Addressing sidewall roughness using dry etching silicon and SiO₂

07/01/2004

The common element in micro-optical electromechanical systems (MOEMS) is the requirement to manipulate the optical signal — light — via surface reflection or gratings. Fabricating structures that do not alter the data that light signals carry brings new demands to etch tool suppliers and process developers. Increasingly, device manufacturers require etch tool suppliers to provide the platform and process capability necessary to allow a wide range of device parameters to be taken into account during the fabrication process.

Use of time-multiplexed plasma etching to produce smooth optical surfaces in silicon is difficult because the process inherently removes "scallops" of material with each process cycle. Our work has involved fundamentally improving the inherent roughness of this process [1–3]. We have also characterized various silicon dioxide dry etching processes that provide through-wafer capability at higher etch rates and aspect ratios than previously reported.

Two types of inductively coupled plasma (ICP) etch sources were used. First, Advanced Silicon Etch (ASE) incorporates a decoupled plasma source (patent pending) that generates a very high-density plasma that diffuses into a separate process chamber. By reducing excess ions that are detrimental to process control, a uniform distribution of fluorine free radicals at a higher density than that available from a conventional ICP source is obtained. The higher fluorine free-radical density enables increased etch rates, typically more than 3× that achieved with a classic Bosch etch process. Reducing the effect of localized depletion of these species improves etch uniformity for many applications.

The second ICP etch source, Advanced Oxide Etch (AOE), uses a planar inductively coupled radio frequency (13.56MHz) plasma coil with multipolar magnetic confinement at the chamber sidewalls and high-rate vacuum pumping. This combination provides ion densities >5×10¹¹cm^-3 at a pressure of 1mtorr in argon, while reducing the mechanical clean frequency to >1000µm of oxide etch. AOE can achieve independent ion energy control through RF biasing of the temperature-controlled substrate electrode.

Smoothing out silicon etch

For silicon etching in optical devices, sidewall quality is critical to device performance. Two approaches have been tried to achieve optically smooth sidewall quality: a switched process based on the classic Bosch process [4] and a process using fluorocarbon plasma in a nonswitched regime at room temperature.

The Bosch process etches via sequential etch and deposition steps using SF_x and C_xF_y plasmas. The etch-to-deposition ratio process parameters determine sidewall roughness (i.e., scallop size). Scallop size depends on cycle times and plasma parameters, such as coil power and pressure, rate of removal of deposited material and the deposition rate of the CxFy layer. By simply reducing the overall cycle times and maintaining the same etch-to-deposition ratio, scallop size is reduced, but this can result in reduced etch rate.

The importance of species transport into and out of the etched feature became apparent: At shorter cycle times, there is less time for etching and deposition to occur, and influences such as gas delivery into the system become more critical. System components that contribute to switching dynamics within the chamber were changed, resulting in an enhanced etch rate without a detrimental effect to sidewall roughness. Further experiments with optimized hardware found that a reduction in etch cycle time reduces etch rate and scallop size. With cycle times <1 sec, however, a time-gas constant effect was observed.

Our conclusion was that with very short switching times, there is no longer a clearly defined etch and deposition cycle, but rather a mixture of process gases. This can lead to bowing of high aspect-ratio (HAR) features.

A smooth-sidewall process was developed that enables the etching of features in optical MEMS without the requirement for <1 sec switching. This process uses patented "parameter ramping" to change process parameters over time, thus reducing sidewall etching without detrimental effects to the etch rate [5, 6]. Figure 1 is a SEM of an etched feature with an AFM RMS sidewall roughness of 8.8nm at the top of the feature.

Figure 1. SEM of an etched feature with an AFM RMS sidewall roughness of 8.8nm at the top of the feature.Click here to enlarge image

When developing smooth-sidewall processes, excess passivation on the sidewall must be avoided because it can disguise scallops and may look as though sidewall roughness is smoother than it actually is, especially if the coating is greater than the depth of the scallops.

Experiments with a nonswitched process for shallow etches at room temperature using a mixture of fluorocarbon precursors fed into a plasma were also conducted. Sidewall roughness measurements have shown RMS values <7nm. The nonswitched process window results in lower etch rates than those achieved using a Bosch-type process, typically, 1–2.5µm/min.

Deepening oxide etch

For applications where etch rate and HAR are not limiting factors, dielectric etch may be carried out using conventional reactive ion etch (RIE) technologies. Recent demands in SiO₂-based micro-optical applications have required substantial improvement in oxide etch rate, high selectivity to mask materials, and an ability to etch substantially narrower features to ever-greater depths without excessive RIE lag.

Three types of SiO₂ etch processes have recently required performance improvement: deep reactive-ion oxide etching, submicron high aspect-ratio oxide etching, and high-rate through-wafer SiO₂ etch.

As aspect ratios increase with etch depths going >20–30µm, the use of conventional process recipes can cause significant problems with etch profiles as a result of trenching, faceting, or bowing [7–10]. To improve deep-etch characteristics, a series of trials using polysilicon masked (optical device patterned) 200mm wafers with a 45µm-thick germanium, p-doped and undoped SiO₂ bilayer were performed. Results indicated that manipulation of the platen power, platen temperature, and concentration of hydrogenated species was important to control the sidewall profile and roughness.

Following a series of statistical optimization tests, a 40µm-deep etch profile with the remnant mask clearly visible above the dielectric was achieved. Despite the change in doping concentration as a function of etch depth, no evidence of a change in sidewall angle could be detected. Sidewall striations within the oxide etch through transfer of mask roughness were minimal. Selectivity over the silicon mask was >25:1 with critical dimension loss <1µm.

Investigation into process requirements for submicron feature size HAR etching of dielectric components also found significant trend differences over conventional isolated waveguide recipes. Alteration of plasma chemistry to control the CF₂:CF₃ ion ratio, reduction in working gas pressure, polymerization-dilution gas flow, and significantly higher reactive-ion energies were all found to alleviate excessive RIE lag effects.

A significant factor with AOE is the utilization of 2000 liter/sec turbo-molecular pumping that allows an operational pressure window from 100mtorr down to 1mtorr. Extension of the mean-free-path of reactive ions by reducing the probability of charge-exchange collisions can be routinely achieved at low pressure. Enhanced ion energies may be delivered by the combined application of up to 1kW of RF-bias power to the substrate and suitable optimization of the chamber configuration. Figure 2 illustrates HAR submicron process results from SiO₂ etch trials using 0.7µm-wide hole patterned, aluminum-metal (0.8µm) masked wafers. A uniform array of smooth sidewall and narrow trenches was formed with no evidence of etch stop or trench closure despite the aspect ratio approaching 12:1.

Figure 2. Array of 0.7µm HAR etched holes (in cooperation with DALSA Semiconductor).Click here to enlarge image

Vertical sidewall characteristics of the HAR etch can be maintained even when feature size is reduced to 0.3µm-wide fused silica ridges (Cr metal mask thickness limited to 70nm). Aspect ratios >10:1 could still be achieved at an etch rate of 540nm/min and a selectivity to the mask of more than 50:1.

HAR dielectric etch approaching submicron scale is also finding application within various photoresist-masked SOI devices. Figure 3 shows a SEM from a two-stage reactive-ion etch process comprising an initial time-multiplexed HAR ASE silicon etch followed by a second step of HAR AOE buried oxide etch. The use of low-pressure, high-energy reactive ion bombardment in combination with controlled plasma polymerization produced an oxide etch with smooth sidewalls, vertical profile, and virtually no critical dimension loss despite a starting aspect ratio of >12:1.

Figure 3. Results from a combined ASE-AOE HAR etch. (Courtesy of Analog Devices, Northern Ireland)Click here to enlarge image

We performed a series of experiments with AOE to investigate and optimize various photoresist- and polysilicon-masked process windows, using 150mm waveguide-patterned wafers (15µm HiPox SiO₂ film). Data from these experiments indicated three dominant process parameters: 13.56MHz platen, coil power, and etchant gas flow. Figure 4 gives oxide etch rate as a function of CF_x etch gas flow while maintaining coil and platen powers constant. Conventional oxide etch used for optical waveguide applications generally perform at 0.5µm/min; in comparison, an average through-wafer etch rate is 1.2µm/min.

Figure 4. Oxide etch rate as a function of CF_x flow rate.Click here to enlarge image

The ability to controllably etch SiO₂ at rates >1µm/min without time-multiplexing enabled us to examine through-wafer etch capability, which was done in collaboration with researchers at the U. of Alabama. High-rate recipes to etch a series of 400µm-thick fused silica and quartz wafers with a ceramic-bonded, pre-etched silicon mask were used. In all cases, the etch process directly followed the original mask angle. The average through-wafer etch rate was 1.2µm/min. Through-wafer etching to a depth of 400µm without performance deficit was also confirmed.

Conclusion

One can significantly reduce sidewall roughness to <10nm RMS using time-multiplexed ASE processing adapted with a combination of hardware and process developments. This capability is applicable to a broad range of silicon-based devices for micro-optical applications.

Enhanced capability and performance of AOE-based SiO₂ processing allows a wide range of micro-optical applications from HAR submicron processing to high-rate, deep through-wafer etching. One can routinely achieve vertical dielectric features at HAR with smooth sidewalls. Through-wafer oxide etching processes with a capability of 1.2µm/min have been developed.

Acknowledgments

ASE is a registered trademark and AOE is a trademark of Surface Technology Systems Plc.

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