Analyzing strained-silicon options for stress-engineering transistors
07/01/2004
Future silicon technology will depend on locally strained silicon channels to squeeze higher currents from each process node. Careful stress engineering can enhance device performance by more than 50%, but there are tradeoffs in processing methods to create strained silicon. Stress-strain analysis, performed with a 3D simulation tool, explores those tradeoffs and efficiencies by running different virtual process flows in Technology CAD (TCAD) software.
Stresses are known to affect bandgap and carrier mobility in silicon. Appropriate stress applied to the channel can significantly improve transistor performance in terms of the Ioff/Ion ratio. Stress can be beneficial or detrimental to the nMOS and pMOS, depending on the stress pattern.
For example, stress resulting from the standard shallow-trench isolation (STI) is known to enhance pMOS performance by up to 20% while simultaneously degrading nMOS performance by about 15%. This shows that it is typically necessary to apply opposite stresses to p-channel and n-channel devices, which could lead to different process steps and geometries for the two device types.
Stress can be introduced intentionally by deposition of a pre-strained layer or it could be due to unintentional stress sources. Unintentional stress is generated as a side effect of oxidation, etch, deposition, silicidation, and thermal steps. The unintentional stress should be considered to determine the overall stress distribution when designing appropriate methods to introduce intentional stress into the device.
Desirable stresses
Due to the inherent mechanical properties of silicon, the stress field generated by a stress source (such as the STI sidewall) penetrates through approximately 200nm of adjacent silicon. Stress decays inversely proportional to distance from the stress source and drops by a factor of three within ~200nm. When several stress sources happen to be within that range, their stress fields overlap. This is why devices at the 180nm technology node and below have significant stress levels due to the overlapping stresses from STI, gate stack, and silicide.
 Figure 1. Cross-section of a 45nm CMOS transistor with SiGe S/D. |
Figure 1 shows the cross-section of a MOSFET with 45nm gate length and SiGe source and drain. Let's consider that we have managed to introduce some stress into the channel and look at the impact of the three stress components along x, y, and z axes on transistor. Table 1 summarizes the impact of 1GPa stress applied along x, y, and z in the channel on the transistor performance. It is based on a simple classic piezoresistance effect [1], yet provides reasonably good description of the stressed devices [2]. The performance modification percentages listed in the table are only approximate, as they reflect the changes in the low field mobility and neglect a variety of other factors. Compressive and tensile stresses cause opposite effects on transistor performance.
Methods to introduce stress
In a typical process flow without stress engineering, stress-field generation is primarily due to the different volume expansion/contraction rates of the adjacent materials during temperature ramps. Stress also is generated by growing oxides and silicides, etching and depositing layers, and introducing dopants into the silicon.
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It is possible to control stress distribution to some extent by depositing pre-strained layers in a way that introduces desirable stress into the channel. While it is hard to measure stress distribution in submicron devices, 2D and 3D stress distribution and its evolution during the process flow can be simulated. We explored stress effects in the 45nm MOSFET with the Taurus-Process simulator that models stresses for semiconductor applications [3].
Figure 2 shows the distribution of the x stress component in the 45nm transistor with 15% Ge in SiGe source/drain (S/D) at the end of the process flow. A uniform compressive stress of ~1GPa is generated in the channel. Such a stress pattern is beneficial to pMOS as was successfully demonstrated in [4], but would be detrimental to nMOS. If this were the only component contributing to stress in the channel, according to Table 1, it would have increased pMOS drain current by 70%.
 Figure 2. Distribution of the x stress component (i.e., in the direction along the channel) in a 45nm MOSFET at the end of the process flow. |
Let's intentionally pre-strain deposited layers so they have 1GPa intrinsic stress. When we do this for the different layers in the transistor and run it through the process flow, we get the average stress in the channel depicted in Fig. 3. It is clear that all methods of introducing stress have an efficiency (ratio of stress in channel to intrinsic stress) <100%. Positive numbers mean that the stress in the channel has the same sign as the stress in the deposited layer. Negative percentage means that the stress in the channel is opposite to the original stress in the deposited layer.
 Figure 3. Efficiency of transferring stress from different sources into the channel. |
Some of the methods possess relatively high stress-transfer efficiency. Notably, SiGe S/D and strained STI transfer slightly more than 50% of their stress into the channel. This helps to introduce significant stress into the channel, while keeping the peak stress low to prevent defect/crack formation.
It is clear that none of these methods creates a purely uniaxial stress, but some of them create stress patterns with one dominant component and therefore come close to uniaxial. For example, STI that is pre-strained to 1GPa tensile stress introduces into the channel 510MPa of tensile stress along the x axis, 60MPa of compressive stress along the y axis, and 120MPa of tensile stress along the z axis.
It is important to make sure that the combined effect of the three stress components (along x, y, and z axes) is still positive and different contributions do not cancel each other out. If several methods are used simultaneously, then certain stress components add up, but some others do not add up, exhibiting very nonlinear interaction.
The obtained percentages are valid for the bulk devices with geometries and process flows similar to those explored here. For a different device geometry, the stress transfer pattern can be completely different. For example, Fig. 4 shows the 3D stress pattern for a 25nm fully depleted SOI (FDSOI) MOSFET with metal gate and mesa isolation. In this case, a complicated 3D stress pattern is formed with significant x, y, and z components. The reported electrical measurements of such nMOS and pMOS devices [5] show that stress enhanced performance of both nMOS and pMOS by ~30%. Figure 4 shows that the distribution of the z stress component is very nonuniform in the channel, varying from 100MPa compressive to 800MPa tensile stress. Stress transfer efficiency from metal gate to the channel is close to 100%. This must be attributed to the specific geometry of this device.
Application of the piezoresistance model to FDSOI MOSFETs significantly underestimates the stress effect for nMOS and pMOS transistors. An alternative, more sophisticated model for stress-enhanced mobility [6] also underestimates the performance enhancement. This means that at this point, existing theory can explain satisfactorily only the cases where one stress component dominates, and the other components are negligible.
Layout implications
The results displayed in Figs. 2 and 3 were obtained with 2D simulation, which implies infinite channel width. For a real device, the channel width is finite and the stress field is affected by the actual channel width in the third dimension. Results of the 3D simulation of the structure with SiGe S/D for different channel widths are summarized in Fig. 5. In the 2D case, both x and z stress components are compressive and rather large: -1000MPa and -350MPa, respectively.
 Figure 5. Effect of device width on average values of x and z stress components in the channel for 45nm MOSFET with SiGe S/D. |
As the channel width shrinks to the values typical for memory, both stress components shift toward tensile stress and become -780MPa and 55MPa, respectively. How does this translate into stress-enhanced performance? For pMOS, the 80nm-wide transistor performs 20% better than the infinitely wide transistor, while for nMOS it becomes about 45% worse than the infinitely wide one.
In 400nm-wide transistors that are typical for logic applications, pMOS gains 20% and nMOS loses 35%, compared to the infinitely wide transistors.
If you change the size of SiGe S/D (i.e., distance from gate to STI) or the size of STI (i.e., distance between two transistors), it will change the stress level in the channel. Therefore, variations in chip layout such as different feature density will introduce variations in stress-enhanced performance across the chip.
Practical recommendations
The summary of stress-engineering effects is presented in Table 2. It is based on piezoresistance model and applies to the particular case of geometry and process flow of 45nm MOSFET transistors explored in this work. Different geometries, process flows, and technology nodes will yield different results.
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Based on Table 2, the best suggestion would be to use SiGe S/D to improve pMOS performance and a tensile cap layer to improve nMOS performance. The other methods can be added to these two as complementary to further enhance device performance.
References
- C.S. Smith, "Piezoresistance Effect in Germanium and Silicon," Phys. Rev., Vol. 94, No. 1, pp. 42–49, 1954.
- S.E. Thompson, et al., "A Logic Nanotechnology Featuring Strained-silicon," IEEE Electron Dev. Lett., Vol. 25, No. 4, pp. 191–193, 2004.
- V. Moroz, et al,, "Modeling the Impact of Stress on Silicon Processes and Devices," Mat. Sci. in Semicond. Processing, Vol. 6, pp. 27–36, 2003.
- T. Ghani, et al., "A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors," Proc. IEDM, pp. 978–980, 2003.
- Z. Krivokapic, et al., "Locally Strained Ultra-thin Channel 25nm Narrow FDSOI Devices with Metal Gate and Mesa Isolation," Proc. IEDM, pp. 445–448, 2003.
- M.V. Fischetti, S.E. Laux, "Band Structure, Deformation Potentials, and Carrier Mobility in Strained Si, Ge, and SiGe Alloys," J. Appl. Phys., Vol. 80, p. 2234, 1996.
Victor Moroz received his PhD in semiconductor physics at the U. of Nizhny Novgorod. He is a principal engineer at Synopsys Inc., 700 E. Middlefield Rd., Mountain View, CA 94043; ph 650/584-5458, fax 650/584-1366, e-mail [email protected].
Xiaopeng Xu received his PhD in engineering from Brown U. He is a staff engineer at Synopsys.
Dipu Pramanik received his PhD in physics from Cornell U., and is responsible for design for yield at Synopsys.
Faran Nouri received her MS in electrical engineering from the U. of Colorado. She leads efforts in process integration, device engineering, and TCAD for the frontend products group at Applied Materials Inc., 3050 Bowers Ave., P.O. Box 58039, Santa Clara, CA 95054-3299; ph 408/584-0258, fax 408/584-1193, e-mail [email protected].
Zoran Krivokapic received his DrSc in electrical engineering from the U. of Ljubljana, Slovenia. He performs research in high-performance logic and nonvolatile memory devices in the strategic technology group at Advanced Micro Devices Inc., One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088-3453; ph 408/749-3236, fax 408/749-3851, e-mail [email protected].