New processes allow InP HBTs to top 150GHz
07/01/2004
Standard compound-semiconductor manufacturing techniques, such as lift-off contact metallization and unique epitaxial structures, while viable for low transistor-count applications, have process yield limitations that prevent increased integration of these submicron devices into ever-smaller circuit dimensions. Emerging applications require the adoption of silicon industry standard processes and device structures to enable volume manufacturing of tens of thousands of active compound semiconductor devices in a single circuit with acceptable yield.
Indium phosphide (InP) is a direct bandgap material with an energy gap that allows the direct generation and detection of light at wavelengths suited for long-distance optical fiber communications. Today, InP is used to manufacture a variety of lasers and photodetectors operating in the 1.3–1.55µm spectral range. Other properties of InP, such as higher electron mobility (~9× SiGe and 2× GaAs) and higher breakdown voltage (~2× SiGe), make it suitable for high-speed and high breakdown-voltage electronic applications.
The second-generation Vitesse indium phosphide (VIP-2) double-heterojunction bipolar transistor (DHBT) has recently been used to demonstrate static-frequency divider circuits operating at 152GHz, the highest flip-flop operation reported to date in any semiconductor technology. This record was accomplished at lower power than similar SiGe circuits that operate at 30% lower speed.
The IC technology used to reach these levels of performance leverages lessons from silicon manufacturing, in which performance improvements over the past decades relied not only on material characteristics, but also on advanced processing capabilities. In general, shrinking transistor dimensions improves the speed of the device; this is also true with InP. Conventional compound-semiconductor manufacturing practices such as lift-off contact metallization, air-bridge interconnect structures, and gold as the interconnect metal, however, are difficult to scale to smaller transistor dimensions and do not easily support multiple levels of interconnect wiring. They also can significantly limit the yield of complex circuits.
Considerable effort has been put into the development of HBTs in InP for applications in RF systems. Promising device performance has been achieved by both R&D and commercial organizations. Novel process and device approaches have been used in many cases to achieve very high Ft and Fmax. High-frequency performance >400GHz Fmax has recently been reported by research teams at the U. of Santa Barbara and the U. of Illinois. Employing lift-off contact metallization and unique epitaxial structures, these approaches are viable for low transistor-count applications, but process yield limitations will prevent increased integration of these submicron devices.
The emerging mixed-signal IC market segment for end applications that include radar signal processing requires a technology that can support several thousand to tens of thousands of active devices in a single circuit with acceptable yield, and produce ICs that operate at clock rates in the 50–100GHz range. Adopting silicon industry standard processing techniques and device structures provides a straightforward means to achieve these goals.
Departing from standard processing techniques
InP substrates and epitaxial material quality have improved significantly over the past several years. Substrates are available in up to 4 in. dia. Semi-insulating material is used for HBT fabrication due to reduced parasitics. MBE-grown epitaxial layers are primarily used to form the active device structures. The low point defect density in available material is routinely <50/cm2, more than adequate for medium-scale ICs with up to tens of thousands of transistors. The most common base dopants are carbon and beryllium — both of which have exhibited stable performance in extensive reliability testing.
The goal of Vitesse's second-generation process development program was to create a process that would not only achieve extremely high-speed transistor and circuit operation, but could also be manufactured routinely with very high yield. To this end, we departed from standard compound-semiconductor processing techniques.
The largest yield limiter identified through experience with VIP-1 (a first-generation mesa HBT process) was lift-off metallization. Especially true with submicron geometries, lift-off metallization is a defect-generating process that has a tendency to leave metal stringers that easily short base and emitter transistor terminals. Furthermore, lift-off for contact metallization requires photolithography.
While submicron features can be repeatably produced with stepper technology, transistor design needs to account for mask overlay margin. Overlay margin associated with a lift-off mask set will result in an increase of parasitic Cbc (total base-collector capicitance).
Other key issues for compound-semiconductor transistor manufacturing include surface passivation, the formation of low-resistance ohmic contacts, and thermal conductivity. Surface passivation is addressed through wide bandgap semiconductors and PECVD dielectrics. No epitaxial regrowth is required in the process, which is important since regrowth is viewed as a significant potential yield limiter. The complete epitaxial structure is grown prior to the start of device fabrication.
Other limitations of the conventional InP HBT device structure were overcome by developing a self-aligned transistor that borrows heavily on CMOS processing techniques. In this new HBT (Fig. 1), the emitter-base contact spacing, the base contact width, and the collector width are all self-aligned (either directly or indirectly) to the 0.35µm emitter. The separation between the emitter and the base contact metal is created by a self-aligned dielectric spacer, which is similar to the standard CMOS spacer that separates the gate from the source/drain regions. The base contact is then formed as a self-aligned metal spacer.
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The thermally stable ohmic contacts are formed using nonalloyed refractory metals and exhibit contact resistance on the order of 10E-7Ω-cm2. The collector is subsequently defined using the base contact metal as a self-aligned mask. These self-aligned features minimize the collector capacitance while making the device very compact and highly scalable. Quaternary and tertiary compound semiconductors are not used in the subcollector to minimize the thermal resistance of the device.
 Figure 2. Ft and Fmax for VIP-2 are both >300GHz. |
Along with lateral scaling of the transistor, the HBT is scaled in the vertical dimension as well. Since carriers in the devices move primarily vertically, scaling the base and collector layer thickness is critical to increasing transistor speed. The collector thickness is reduced to 1500Å in VIP-2, compared to 3000Å in VIP-1. This reduces the transit time through the collector, tc, but it also increases the intrinsic capacitance, Cbci, proportionally. This increase in intrinsic Cbci is more than offset by the significant reduction in extrinsic Cbcx resulting from the self-aligned spacer process in VIP-2. Epi grading of the base semiconductor is employed to add a drift component to the diffusion of carriers across the base that reduces the base transit time. The RF performance of the VIP-2 transistors benefits greatly from all of the parasitic reduction. The table summarizes many of the critical improvements in transistors.
Performance
RF performance across a 4-in. wafer is routinely >300GHz for Ft and Fmax (Fig. 2) and is achieved with a breakdown voltage of 4.5V, more than twice that of advanced SiGe transistors (Fig. 3). This allows InP HBTs to address RF circuits with higher power requirements.
 Figure 3. The breakdown voltage of the VIP-2 devices is about 4.5V, more than twice that of high-speed SiGe HBT technologies. |
Medium-scale ICs with tens of thousands of transistors and operating at >50GHz clock rates require compact layout only achievable with multiple levels of interconnect metallization. In state-of-the-art silicon CMOS circuits with tens of millions of transistors, eight or more levels of interconnect are common. With the VIP-2 process aimed at medium-scale ICs, we achieved optimal benefit at four levels of interconnect metal. Compared to VIP-1 with three levels of interconnect metal, interconnect scaling and transistor scaling allow us to reduce circuit cell area by ~50% generation over generation. Stacked vias also provide a significant benefit in circuit design.
An integrated process design kit developed in the Cadence EDA environment enables high-speed circuit design. External designers at BAE Systems used the Vitesse design kit to design and simulate record 152GHz static-frequency divider circuits. Shown in Fig. 4 is the divide-by-2 output of a circuit that was fed by a 152GHz source.
Conclusion
The VIP-2 process represents an aggressive scaling of InP HBTs with significant departure away from conventional III-V manufacturing practices. It is not only a manufacturable process that produces very high-speed transistors with >300GHz Ft and Fmax, but the process design kit allows for design, simulation, and layout of very high-speed circuits such as flip-flops that operate at >150GHz. These very fast transistors will enable frequency-agile digital synthesis of waveforms for radar and telecommunications.
Acknowledgments
VIP-1 and VIP-2 are trademarks of Vitesse Semiconductor Corp.
Minh Le received his SB and SM degrees from MIT, and is currently the indium phosphide foundry manager at Vitesse Semiconductor Corp., 741 Calle Plano, Camarillo, CA 93012; ph 805/388-3700, e-mail [email protected].