Issue



Integrating a nonporous low-k (k = 2.2) film


07/01/2004







Several low-k (≤2.7) dielectric films will be examined in view of critically important properties required for IC integration, reliability, and IC packaging. Additionally, integration results of a nonporous, CVD-manufactured film (via transport polymerization) with a k = 2.2 will be disclosed.

Recently, an author pointed out that the engineering of a manufacturable interconnect structure with new low-k materials and processes remains one of the three key challenges in interconnect technology [1]. He also revealed that the new 2003 edition of the International Technology Roadmap for Semiconductors (ITRS) has rolled back the requirement for the bulk dielectric constant, k, from 2.4 to 2.7 for the 90 to 65nm technology nodes.

The table on p. 70 summarizes comparative properties for some low-k (≤2.7) films currently available to the industry. Black Diamond is derived from plasma polymerization of siloxane and has a general composition of SiOxCyHz. SiLK is a spin-on polymer consisting of carbon, hydrogen, and oxygen. LKD 5109 is a porous MSQ. FAR 2.2, a polymer consisting of only C, H, and F, is obtained via transport polymerization of reactive diradical intermediates in a low-pressure, nonplasma deposition system [2].

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For IC applications, low-k integration and packaging issues have to be successfully addressed. The spin-on organic polymer and the nonporous plasma CVD siloxane dielectric films that have k values between 2.6–2.7 could not be used in volume production for 130nm IC applications because of delamination problems encountered during chip packaging. These materials failed to provide sufficient packaging yield due to the excessive coefficient of thermal expansion (CTE) mismatch between the films (50–60ppm/°C) and copper (17ppm/°C).

There is no improved spin-on organic polymer that can offer higher Young's modulus and lower CTE. For the plasma CVD siloxane films, however, reducing the C and H contents has resulted in higher cross-linking density, thus higher Young's modulus and lower CTE. The resulting film's k value will increase from 2.7 to 2.95–3.0, and when integrating this film, redundant vias will have to be added to avoid "collapsed vias" for 90nm IC applications [3].

Porous low-k (<2.7) films also encountered problems both in integration and packaging. In order to lower k value to <2.6, more than 30% of porosity will have to be incorporated into previously existing films such as SiO2 (k = 4.0) and MSQ (k =3.2) [4]. When a low-k film consists of a percolation threshold above ~30% porosity, the micro-pores become interconnected, forming channels inside the film; these channels are connected to the film surfaces.

The IC industry's general frustration over trying to integrate porous low-k materials has been revealed in a recent article [5]. The low-k films based on porous MSQ (p-MSQ) show sidewall damage and carbon depletion after plasma etching, and stress voiding after CMP. Surface pores on the etched films could not be covered even using atomic layer deposition (ALD) for the barrier layer, resulting in pinholes in the barrier layer. Furthermore, the pores in p-MSQ have been attributed as inherent "electrical defects" [6].

Properties of FAR 2.2

The nonporous FAR 2.2 film has a high thermal and dimensional stability that can only be obtained via the crystallization during a polymerization (CDP) process [2, 7, 8] and under proper processing conditions. TEM analysis shows evidence of its nonporosity from the cross-section view of the film on a Si wafer [8].

Because the film consists only of C, H, and F, it will not absorb water — an inherent hydrophobic property, as can be seen in a thermal decomposition scan (TDS); its leakage current is very low compared to other low-k materials containing oxygen [2]. Other notable electrical properties include:

  • dielectric breakdown strength up to 7.6MV/cm at 25°C and 1.8MV/cm at 200°C;
  • time-dependent dielectric breakdown (TDDB) strength at 200°C and 1.5MV/cm over 1 hr; and
  • dielectric constant that does not change after thermal cycling at temperatures up to 400°C.

The C-F bonds in the film have a chemical bonding strength as high as the Si-F bonds in the FSG (k = 3.5) film currently used in production of ICs at the 130nm node. The dielectric film is stable at temperatures as high as 450°C [7]. Additional studies using FTIR and XPS analyses confirmed that the chemical composition remains unchanged after annealing the film for 2.5 hrs at 425°C in inert ambient conditions.

RBS and SIM analyses indicate that the Ta/FAR 2.2/Si stack, after annealing at 350°C for 30 min, shows no fluorine diffusion into the Ta, nor Ta corrosion by fluorine. The depth profile of the stack, obtained from RBS results, is shown in Fig. 1.


Figure 1. Depth profile of a Ta/FAR 2.2/Si sample annealed at 350??C as derived from RBS.
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Young's modulus has been measured by the nano-indentation method on films ranging in thickness from 0.5–2.0µm, and can be as high as 12GPa [8]. With such Young's modulus values, more robust CMP processes can be applied at higher downward pressure without delamination [9], resulting in shorter CMP times and higher process yields.

The stress curve shown in Fig. 2 was measured using a 250nm film on a very thin Si substrate. The top heating and bottom cooling curves show no hysteresis and can be reproduced over several thermal cycles (not shown here for clarity), indicative of no change in either CTE or Young's modulus after thermal cycling.


Figure 2. Film stress on a Si wafer as a function of temperature.
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From the slope of the stress curve (Fig. 2) and the Young's modulus of the film, the in-plane CTE can be estimated using the following equation:

d(Residual Stress)/dT =
Young's modulus [(CTE)1 - (CTE)2] dT/(1-ν)

where (CTE)2 is 2.48ppm/°C for a Si wafer and ν is the Poisson ratio of the film. Assuming ν = 0.34, the result suggests that the CTE should be <20ppm/°C, even when taking into account that Young's modulus could be >12GPa in the xy-plane. This value is closely matched to that of copper (17ppm/°C), ensuring dimensional stability of the interconnect stacks during the integration and packaging processes.

Integration solutions

Two integration structures were evaluated using FAR 2.2: single damascene (SD) and hybrid dual damascene (HDD).

Due to the presence of fluorine in the low-k film, some unique processes and tool features are required for its successful integration into both single- and dual-damascene low-k/copper structures. Some of these include a deposition system for making a composite low-k film that has a surface chemistry compatible with etch and cap layer processes, post-deposition annealing, and post-plasma etching surface repairing processes to stabilize the film.

Without breaking vacuum, a deposition system is used to make the composite film chemically bonded to Si-containing substrates. The adhesion strength between FAR 2.2 and SiO2, SiC, and SiOxCyHz films (i.e., barrier layer, cap layer, and etch stop) used in IC integration can be greatly enhanced. For instance, the adhesion strength of a FAR 2.2/SiO2/Si stack can be as high as 14J/m2.

Plasma etching of the low-k film can be performed under similar conditions employed for etching other organic films such as SiLK, and patterning it can be easily done using forming gas, or H2, without leaving residues. Proper post-annealing process steps and conditions have been developed to amend the compositional changes and re-stabilize etched surfaces for a stable barrier metal-to-low-k interface. The combination of these processes and a robust CMP process has resulted in reliable damascene structures.

If ICs in the future are fabricated using only the processes for SD, then more processing steps would be needed to build 8–9 low-k/Cu stacks in an IC. However, the SD solution may provide higher integration yields. At the 130nm node, some Japanese companies have used SD for fabricating ICs.

Recently, a number of companies [10–12] are pursuing the HDD integration scheme where the etch stop layer is eliminated. To employ the HDD scheme, two low-k films having sufficiently different etch rates under two etching chemistries are required. The use of an organic low-k/inorganic low-k stack becomes an obvious choice.

The dielectric constant of the etch stop layer is normally higher (k = 3.5–5) than the current low-k (≤2.7) materials, so the resulting effective dielectric constant, keff, in a conventional (low-k/etch stop/low-k) stack, or monolithic dual damascene (MDD), is higher than the bulk k value of the low-k film. Therefore, a HDD can result in a lower keff, in addition to potentially eliminating the need for another toolset to deposit the etch stop.

The FAR 2.2 dielectric film has been integrated into both an SD and an HDD/Cu structure (a FAR 2.2 via and a p-MSQ line) in which the keff = 2.6 [10]. In contrast, when only the p-MSQ (k = 2.2) was used in an MDD/Cu structure, the resulting keff is 2.85 [9].

Alternatively, the FAR 2.2 dielectric film can be used in combination with another nonporous CVD low-k (≤2.7) film in the HDD/Cu structure with the added advantage of being able to deposit both films on the same platform. For instance, a HDD/Cu structure using a SiCOH-via and a FAR 2.2-line could be manufactured to avoid the CTE mismatch problem encountered when a SiCOH type low-k film is used alone in the MDD/Cu structure. The effect of CTE mismatch in a low-k/copper line interface is more pronounced due to longer copper lines in the xy-plane, in contrast to the short via depth.

In principle, a similar advantage in the MDD/Cu process can be achieved if a CVD low-k deposition system can also deposit an etch stop. In current commercial plasma low-k systems, the low-k film and the etch stop can both be generated from plasma polymerizations of a siloxane, but under different processing conditions, resulting in a compositionally different film.

A similar approach has been demonstrated for FAR 2.2 in a nonplasma CVD deposition system. In the future, the entire stack of dielectric film/etch stop/dielectric film can be prepared in the same deposition system without breaking vacuum. This composite-dielectric deposition process is most desirable in mass production. Integration of the MDD structure is currently underway at two major semiconductor consortia.

Conclusion

A nonporous CVD film with k = 2.2 has been obtained via a transport polymerization process. The film (FAR 2.2) possesses a high Young's modulus of up to 12GPa, and has an estimated xy-CTE as low as 20ppm/°C and high thermal stability up to 425°C for several hours. The integration processes for the film have been demonstrated using single-damascene and hybrid dual-damascene processes that resulted in a keff of 2.60.

Acknowledgments

The authors would like to thank Drs. S. Ogawa and N. Kaji at Selete, Japan; Dr. T. Fukuda of ASET, Japan; and Prof. T.-M. Lu at Rensselaer Polytechnic Institute, New York, for providing some of the data and valuable discussions. The authors would also like to thank Dr. D. Lam of the David Lam Group for critique and comments.

Black Diamond is a trademark of Applied Materials. SiLK is a trademark of the Dow Chemical Co. LKD is a trademark of JSR Microelectronics. FAR 2.2 is a trademark of Dielectric Systems Inc.

References

  1. C. Case, "New ITRS Target k Values, Structures, and Global Wiring," Solid State Technology, Jan. 2004, p. 47.
  2. C.J. Lee, A. Kumar, A. Ghanbari, "Plain Talk on Low-k Dielectrics," Solid State Technology, June 2003 (and references therein).
  3. D. Lammers, "TSMC Reworks Low-k Process," EETimes, April 26, 2004, p.1.
  4. T. Rantala, W. McLaughlin, J.S. Reid, D. Beery, N.P. Hacker, "The Case for Nonporous Low-k Dielectrics," Solid State Technology, Dec. 2003.
  5. K. Derbyshire, "High Frustration Over Low-k," Semiconductor Manufacturing, October 2003.
  6. L. Peters, "How Low-k Porosity Affects Interconnect Reliability," Semiconductor International, June 2003.
  7. A. Kumar, C. Lee, "Nonporous Low-k Route to 65nm and Beyond," AVS Thin Film User Group California Chapter Seminar, Oct. 2003.
  8. N. Kaji, S. Ogawa, "Nonporous Fluorinated Arylene Film of k = 2.2 with High Young's modulus and Adhesion for Cu/Low-k Interconnect," ADMETA Conference 2003, Tokyo, Japan.
  9. Selete Spring Report 2003 (http://www.selete.co.jp).
  10. S. Sone, et al., "Impacts of High Modulus Ultra Low-k/Cu 300mm Wafer Integration for 65nm Technology Node and Beyond," VLSI Symposium 2003.
  11. T. Usami, H. Nanbu, K. Sugai, M. Tagami, H. Miyamoto, "Stopper-less Hybrid Low-k/Cu DD structure fabrication combined with Low-k CMP," IITC, 2002.
  12. Kajita, et al., "Highly Reliable Cu/Low-k Dual-Damascene Interconnect Technology with Hybrid (PAE/SiOC) Dielectrics for 65nm Node High Performance," eDRAM, IITC, 2003.

Chung J. Lee received his PhD in physical chemistry from RPI and is president of Dielectric Systems Inc., 45500 Northport Loop West, Fremont, CA 94538; ph 510/979-0900; fax 510/979-1237; e-mail [email protected].

Atul Kumar received his PhD in physics from SUNY and is senior director, process development, at Dielectric Systems Inc.